263 lines
8.2 KiB
Verilog
263 lines
8.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; Loos OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE PoosIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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module axi_hdmi_rx (
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// hdmi interface
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hdmi_clk,
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hdmi_data,
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// dma interface
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dma_clk,
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dma_valid,
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dma_data,
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dma_ovf,
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dma_sync,
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// processor interface
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rresp,
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s_axi_rdata,
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s_axi_rready,
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// debug interface (chipscope)
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hdmi_dbg_data);
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// parameters
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parameter PCORE_ID = 0;
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// hdmi interface
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input hdmi_clk;
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input [15:0] hdmi_data;
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// vdma interface
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output dma_clk;
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output dma_valid;
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output [63:0] dma_data;
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input dma_ovf;
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output dma_sync;
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// processor interface
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input s_axi_aresetn;
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input s_axi_aclk;
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input s_axi_awvalid;
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input [31:0] s_axi_awaddr;
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output s_axi_awready;
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input s_axi_wvalid;
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input [31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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input s_axi_bready;
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input s_axi_arvalid;
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input [31:0] s_axi_araddr;
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output s_axi_arready;
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output s_axi_rvalid;
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output [ 1:0] s_axi_rresp;
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output [31:0] s_axi_rdata;
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input s_axi_rready;
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// debug interface
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output [61:0] hdmi_dbg_data;
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reg [31:0] up_scratch = 'h0;
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reg up_packed = 'd0;
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reg up_bgr = 'd0;
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reg up_tpg_enable = 'd0;
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reg up_csc_bypass = 'd0;
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reg up_edge_sel = 'd0;
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reg up_enable = 'd0;
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reg [15:0] up_vs_count = 'd0;
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reg [15:0] up_hs_count = 'd0;
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reg [ 3:0] up_status = 'd0;
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reg [31:0] up_rdata = 'd0;
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wire [31:0] up_rdata_s;
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wire [31:0] up_wdata_s;
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wire [13:0] up_waddr_s;
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wire [13:0] up_raddr_s;
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wire up_wreq_s;
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wire up_rreq_s;
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wire up_wack_s;
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wire up_rack_s;
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wire up_hdmi_hs_mismatch;
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wire up_hdmi_vs_mismatch;
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wire [15:0] up_hdmi_hs;
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wire [15:0] up_hdmi_vs;
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wire hdmi_hs_count_mismatch_s;
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wire hdmi_hs_count_update;
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wire [15:0] hdmi_hs_count_s;
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wire hdmi_vs_count_mismatch_s;
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wire hdmi_vs_count_update;
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wire [15:0] hdmi_vs_count_s;
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wire hdmi_tpm_oos_s;
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wire hdmi_oos_s;
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wire hdmi_oos_hs_s;
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wire hdmi_oos_vs_s;
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wire hdmi_wr_s;
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wire [64:0] hdmi_wdata_s;
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wire up_hdmi_tpm_oos;
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wire up_hdmi_oos;
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wire hdmi_up_edge_sel_s;
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wire [15:0] hdmi_up_hs_count_s;
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wire [15:0] hdmi_up_vs_count_s;
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wire hdmi_up_csc_bypass_s;
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wire hdmi_up_tpg_enable_s;
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wire hdmi_up_packed_s;
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wire hdmi_rst_s;
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wire hdmi_up_bgr_s;
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up_axi i_up_axi (
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.up_rstn(s_axi_aresetn),
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.up_clk(s_axi_aclk),
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.up_axi_awvalid(s_axi_awvalid),
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.up_axi_awaddr(s_axi_awaddr),
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.up_axi_awready(s_axi_awready),
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.up_axi_wvalid(s_axi_wvalid),
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.up_axi_wdata(s_axi_wdata),
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.up_axi_wstrb(s_axi_wstrb),
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.up_axi_wready(s_axi_wready),
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.up_axi_bvalid(s_axi_bvalid),
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.up_axi_bresp(s_axi_bresp),
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.up_axi_bready(s_axi_bready),
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.up_axi_arvalid(s_axi_arvalid),
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.up_axi_araddr(s_axi_araddr),
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.up_axi_arready(s_axi_arready),
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.up_axi_rvalid(s_axi_rvalid),
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.up_axi_rresp(s_axi_rresp),
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.up_axi_rdata(s_axi_rdata),
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.up_axi_rready(s_axi_rready),
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.up_rreq(up_rreq_s),
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.up_wreq(up_wreq_s),
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.up_raddr(up_raddr_s),
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.up_waddr(up_waddr_s),
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.up_wdata(up_wdata_s),
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.up_rdata(up_rdata_s),
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.up_rack(up_rack_s),
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.up_wack(up_wack_s));
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up_hdmi_rx i_up_hdmi_rx (
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.hdmi_clk (hdmi_clk),
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.hdmi_rst (hdmi_rst_s),
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.hdmi_up_hs_count (hdmi_up_hs_count_s),
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.hdmi_up_vs_count (hdmi_up_vs_count_s),
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.hdmi_up_edge_sel (hdmi_up_edge_sel_s),
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.hdmi_up_csc_bypass (hdmi_up_csc_bypass_s),
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.hdmi_up_tpg_enable (hdmi_up_tpg_enable_s),
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.hdmi_up_packed (hdmi_up_packed_s),
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.hdmi_up_bgr (hdmi_up_bgr_s),
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.hdmi_hs_mismatch (hdmi_hs_count_mismatch_s),
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.hdmi_hs (hdmi_hs_count_s),
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.hdmi_vs_mismatch (hdmi_vs_count_mismatch_s),
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.hdmi_vs (hdmi_vs_count_s),
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.hdmi_oos_hs (hdmi_oos_hs_s),
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.hdmi_oos_vs (hdmi_oos_vs_s),
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.hdmi_tpm_oos (hdmi_tpm_oos_s),
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.dma_ovf (dma_ovf),
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.up_clk (s_axi_aclk),
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.up_rstn (s_axi_aresetn),
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.up_rdata (up_rdata_s),
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.up_wdata (up_wdata_s),
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.up_waddr (up_waddr_s),
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.up_raddr (up_raddr_s),
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.up_wreq (up_wreq_s),
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.up_rreq (up_rreq_s),
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.up_wack (up_wack_s),
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.up_rack (up_rack_s));
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assign dma_clk = hdmi_clk;
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assign dma_data = hdmi_wdata_s[63:0];
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assign dma_sync = hdmi_wdata_s[64];
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assign dma_valid = hdmi_wr_s;
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// hdmi interface
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axi_hdmi_rx_core i_hdmi_rx_core (
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.hdmi_clk(hdmi_clk),
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.hdmi_rst (hdmi_rst_s),
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.hdmi_data(hdmi_data),
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.hdmi_hs_count_mismatch(hdmi_hs_count_mismatch_s),
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.hdmi_hs_count_update(hdmi_hs_count_update),
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.hdmi_hs_count(hdmi_hs_count_s),
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.hdmi_vs_count_mismatch(hdmi_vs_count_mismatch_s),
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.hdmi_vs_count_update(hdmi_vs_count_update),
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.hdmi_vs_count(hdmi_vs_count_s),
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.hdmi_tpm_oos(hdmi_tpm_oos_s),
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.hdmi_oos_hs(hdmi_oos_hs_s),
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.hdmi_oos_vs(hdmi_oos_vs_s),
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.hdmi_wr(hdmi_wr_s),
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.hdmi_wdata(hdmi_wdata_s),
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.hdmi_up_edge_sel(hdmi_up_edge_sel_s),
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.hdmi_up_hs_count(hdmi_up_hs_count_s),
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.hdmi_up_vs_count(hdmi_up_vs_count_s),
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.hdmi_up_csc_bypass(hdmi_up_csc_bypass_s),
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.hdmi_up_tpg_enable(hdmi_up_tpg_enable_s),
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.hdmi_up_packed(hdmi_up_packed_s),
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.hdmi_up_bgr(hdmi_up_bgr_s),
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.debug_data(hdmi_dbg_data));
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endmodule
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