145 lines
3.9 KiB
Tcl
145 lines
3.9 KiB
Tcl
# ip
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create axi_dmac
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adi_ip_files axi_dmac [list \
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"$ad_hdl_dir/library/common/sync_bits.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"address_generator.v" \
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"data_mover.v" \
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"request_arb.v" \
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"request_generator.v" \
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"response_handler.v" \
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"axi_register_slice.v" \
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"2d_transfer.v" \
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"dest_axi_mm.v" \
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"dest_axi_stream.v" \
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"dest_fifo_inf.v" \
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"src_axi_mm.v" \
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"src_axi_stream.v" \
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"src_fifo_inf.v" \
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"splitter.v" \
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"response_generator.v" \
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"axi_dmac.v" \
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"axi_dmac_constr.xdc" ]
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adi_ip_properties axi_dmac
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adi_ip_constraints axi_dmac "axi_dmac_constr.xdc" "late"
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adi_ip_add_core_dependencies { \
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analog.com:user:util_axis_resize:1.0 \
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analog.com:user:util_axis_fifo:1.0 \
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}
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adi_add_bus "s_axis" "slave" \
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"xilinx.com:interface:axis_rtl:1.0" \
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"xilinx.com:interface:axis:1.0" \
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[list {"s_axis_ready" "TREADY"} \
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{"s_axis_valid" "TVALID"} \
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{"s_axis_data" "TDATA"} \
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{"s_axis_user" "TUSER"} ]
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adi_add_bus_clock "s_axis_aclk" "s_axis"
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adi_add_bus "m_axis" "master" \
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"xilinx.com:interface:axis_rtl:1.0" \
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"xilinx.com:interface:axis:1.0" \
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[list {"m_axis_ready" "TREADY"} \
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{"m_axis_valid" "TVALID"} \
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{"m_axis_data" "TDATA"} ]
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adi_add_bus_clock "m_axis_aclk" "m_axis"
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adi_set_bus_dependency "m_src_axi" "m_src_axi" \
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 0)"
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adi_set_bus_dependency "m_dest_axi" "m_dest_axi" \
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 0)"
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adi_set_bus_dependency "s_axis" "s_axis" \
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 1)"
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adi_set_bus_dependency "m_axis" "m_axis" \
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 1)"
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adi_set_ports_dependency "fifo_rd" \
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 2)"
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# These are in the design to keep the Altera tools happy which can't handle
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# uni-directional AXI interfaces. The Xilinx tools can and do a better job when
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# they know that the interface is uni-directional, so disable the ports.
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set dummy_axi_ports [list \
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"m_dest_axi_arvalid" \
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"m_dest_axi_arready" \
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"m_dest_axi_araddr" \
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"m_dest_axi_arlen" \
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"m_dest_axi_arsize" \
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"m_dest_axi_arburst" \
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"m_dest_axi_arcache" \
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"m_dest_axi_arprot" \
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"m_dest_axi_rready" \
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"m_dest_axi_rvalid" \
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"m_dest_axi_rresp" \
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"m_dest_axi_rdata" \
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"m_src_axi_awvalid" \
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"m_src_axi_awready" \
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"m_src_axi_awvalid" \
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"m_src_axi_awaddr" \
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"m_src_axi_awlen" \
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"m_src_axi_awsize" \
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"m_src_axi_awburst" \
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"m_src_axi_awcache" \
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"m_src_axi_awprot" \
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"m_src_axi_wvalid" \
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"m_src_axi_wready" \
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"m_src_axi_wvalid" \
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"m_src_axi_wdata" \
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"m_src_axi_wstrb" \
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"m_src_axi_wlast" \
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"m_src_axi_bready" \
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"m_src_axi_bvalid" \
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"m_src_axi_bresp" \
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]
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foreach p $dummy_axi_ports {
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adi_set_ports_dependency $p "0"
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}
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adi_add_bus "fifo_wr" "slave" \
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"analog.com:interface:fifo_wr_rtl:1.0" \
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"analog.com:interface:fifo_wr:1.0" \
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{ \
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{"fifo_wr_en" "EN"} \
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{"fifo_wr_din" "DATA"} \
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{"fifo_wr_overflow" "OVERFLOW"} \
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{"fifo_wr_sync" "SYNC"} \
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{"fifo_wr_xfer_req" "XFER_REQ"} \
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}
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adi_add_bus_clock "fifo_wr_clk" "fifo_wr"
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adi_set_bus_dependency "fifo_wr" "fifo_wr" \
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 2)"
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adi_add_bus "fifo_rd" "slave" \
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"analog.com:interface:fifo_rd_rtl:1.0" \
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"analog.com:interface:fifo_rd:1.0" \
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{
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{"fifo_rd_en" "EN"} \
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{"fifo_rd_dout" "DATA"} \
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{"fifo_rd_valid" "VALID"} \
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{"fifo_rd_underflow" "UNDERFLOW"} \
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}
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adi_add_bus_clock "fifo_rd_clk" "fifo_rd"
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adi_set_bus_dependency "fifo_rd" "fifo_rd" \
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"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 2)"
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foreach port {"m_dest_axi_aresetn" "m_src_axi_aresetn" "s_axis_valid" \
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"s_axis_data" "m_axis_ready" "fifo_wr_en" "fifo_wr_din" "fifo_rd_en"} {
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set_property DRIVER_VALUE "0" [ipx::get_ports $port]
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}
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foreach port {"s_axis_user" "fifo_wr_sync"} {
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set_property DRIVER_VALUE "1" [ipx::get_ports $port]
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}
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ipx::save_core [ipx::current_core]
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