pluto_hdl_adi/library/xilinx/common/ad_lvds_clk.v

89 lines
3.3 KiB
Verilog

// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_lvds_clk #(
parameter DEVICE_TYPE = 0) (
input rst,
output locked,
input clk_in_p,
input clk_in_n,
output clk);
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
// wires
wire clk_ibuf_s;
// defaults
assign locked = 1'b1;
// instantiations
IBUFGDS i_rx_clk_ibuf (
.I (clk_in_p),
.IB (clk_in_n),
.O (clk_ibuf_s));
generate
if (DEVICE_TYPE == VIRTEX6) begin
BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf (
.CLR (1'b0),
.CE (1'b1),
.I (clk_ibuf_s),
.O (clk));
end else begin
BUFG i_clk_gbuf (
.I (clk_ibuf_s),
.O (clk));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************