282 lines
7.4 KiB
Verilog
282 lines
7.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2017(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1 ns / 1 ns
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module fir_decim #(
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parameter USE_DSP48E = 1
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) (
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input clk,
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input clk_enable,
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input reset,
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input signed [11:0] filter_in,
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output reg signed [25:0] filter_out,
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output reg ce_out
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);
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localparam signed [11:0] coeffphase1_1 = 12'b000011010101; //sfix12_En11
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localparam signed [11:0] coeffphase1_2 = 12'b011011110010; //sfix12_En11
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localparam signed [11:0] coeffphase1_3 = 12'b110000111110; //sfix12_En11
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// We know that clk_enable is asserted at most every 5th clock cycle and the
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// output is decimated by two. So we have 10 clock cycles to compute the
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// result. That's plenty of time considering that there are only 6
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// coefficients.
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reg active = 1'b0;
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reg active_d1 = 1'b0;
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reg active_d2 = 1'b0;
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reg [1:0] count = 2'b00;
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reg phase = 1'b1;
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reg ready = 1'b0;
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reg [3:0] storage0[0:11];
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reg [3:0] storage1[0:11];
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reg signed [11:0] data0;
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reg signed [11:0] data1;
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reg signed [11:0] coeff;
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wire signed [25:0] sum;
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integer j;
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initial begin
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for (j = 0; j < 12; j = j + 1) begin
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storage0[j] <= 'h00;
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storage1[j] <= 'h00;
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end
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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phase <= 1'b1;
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end else begin
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if (clk_enable == 1'b1) begin
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phase <= phase + 1'b1;
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end
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end
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end
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always @(posedge clk) begin
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if (clk_enable == 1'b1 && phase == 1'b1) begin
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active <= 1'b1;
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end else if (count == 'h2) begin
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active <= 1'b0;
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end
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active_d1 <= active;
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active_d2 <= active_d1;
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end
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always @(posedge clk) begin
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if (active == 1'b1) begin
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case (count)
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'h2: count <= 'h0;
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default: count <= count + 1'b1;
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endcase
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end
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end
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always @(posedge clk) begin
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if (active_d1 == 1'b0 && active_d2 == 1'b1) begin
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ready <= 1'b1;
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end else begin
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ready <= 1'b0;
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end
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end
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generate
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genvar i;
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for (i = 0; i < 12; i = i + 1) begin
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always @(posedge clk) begin
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if (clk_enable == 1'b1) begin
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if (phase == 1'b0) begin
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storage0[i] <= {storage0[i][2:0],filter_in[i]};
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end
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if (phase == 1'b1) begin
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storage1[i] <= {storage1[i][2:0],filter_in[i]};
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end
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end
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end
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always @(*) begin
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data0[i] <= storage0[i][2-count];
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data1[i] <= storage1[i][count];
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end
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end
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endgenerate
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always @(*) begin
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case (count)
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'h0: coeff <= coeffphase1_1;
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'h1: coeff <= coeffphase1_2;
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'h2: coeff <= coeffphase1_3;
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default: coeff <= 'h00;
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endcase
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end
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generate if (USE_DSP48E) begin
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wire [47:0] _sum;
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wire [6:0] opmode = {1'b0,active_d2,5'b00101};
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// Can't exceed 26 bit.
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assign sum = _sum[43:18];
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// MAC with pre-adder
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DSP48E1 #(
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.ACASCREG (0),
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.ADREG (1),
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.ALUMODEREG (0),
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.AREG (0),
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.AUTORESET_PATDET ("NO_RESET"),
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.A_INPUT ("DIRECT"),
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.BCASCREG (1),
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.BREG (1),
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.B_INPUT ("DIRECT"),
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.CARRYINREG (0),
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.CARRYINSELREG (0),
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.CREG (0),
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.DREG (0),
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.INMODEREG (0),
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.MASK (48'h3fffffffffff),
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.MREG (1),
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.OPMODEREG (1),
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.PATTERN (48'h000000000000),
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.PREG (1),
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.SEL_MASK ("MASK"),
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.SEL_PATTERN ("PATTERN"),
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.USE_DPORT ("TRUE"),
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.USE_MULT ("MULTIPLY"),
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.USE_PATTERN_DETECT ("NO_PATDET"),
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.USE_SIMD ("ONE48"))
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i_dsp_mac (
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.CLK (clk),
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.A ({5'h0,data0[11],data0,12'h0}), // MSB aligned to 24-bit, 25th bit signed extended
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.B ({coeff,6'b0}),
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.C (48'h00),
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.D ({data1[11],data1,12'h0}),
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.MULTSIGNIN (1'b0),
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.CARRYIN (1'b0),
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.CARRYCASCIN (1'b0),
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.ACIN (30'h0),
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.BCIN (18'h0),
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.PCIN (48'h0),
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.P (_sum),
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.MULTSIGNOUT (),
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.CARRYOUT (),
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.CARRYCASCOUT (),
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.ACOUT (),
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.BCOUT (),
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.PCOUT (),
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.ALUMODE (4'b0000),
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.CARRYINSEL (3'h0),
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.INMODE (5'b00100),
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.OPMODE (opmode),
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.PATTERNBDETECT (),
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.PATTERNDETECT (),
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.OVERFLOW (),
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.UNDERFLOW (),
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.CEA1 (1'b0),
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.CEA2 (1'b0),
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.CEAD (active),
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.CEALUMODE (1'b0),
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.CEB1 (1'b0),
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.CEB2 (active),
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.CEC (1'b0),
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.CECARRYIN (1'b0),
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.CECTRL (active),
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.CED (1'b0),
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.CEINMODE (1'b0),
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.CEM (active_d1),
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.CEP (active_d2),
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.RSTA (1'b0),
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.RSTALLCARRYIN (1'b0),
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.RSTALUMODE (1'b0),
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.RSTB (1'b0),
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.RSTC (1'b0),
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.RSTCTRL (1'b0),
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.RSTD (1'b0),
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.RSTINMODE (1'b0),
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.RSTM (1'b0),
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.RSTP (1'b0)
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);
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end else begin
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reg signed [25:0] _sum = 'h00;
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reg signed [12:0] pre_adder;
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reg signed [11:0] coeff_d1;
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reg signed [23:0] product = 'h00;
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assign sum = _sum;
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always @(posedge clk) begin
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if (active == 1'b1) begin
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pre_adder <= data0 + data1;
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coeff_d1 <= coeff;
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end
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if (active_d1 == 1'b1) begin
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product <= coeff_d1 * pre_adder;
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end
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if (reset == 1'b1 || ready == 1'b1) begin
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_sum <= 'h00;
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end else if (active_d2 == 1'b1) begin
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_sum <= _sum + product;
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end
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end
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end
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endgenerate
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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ce_out <= 1'b0;
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end else begin
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ce_out <= ready;
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end
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end
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always @(posedge clk) begin
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if (ready == 1'b1) begin
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filter_out <= sum;
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end
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end
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endmodule
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