576 lines
23 KiB
Tcl
576 lines
23 KiB
Tcl
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package require qsys 14.0
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source ../../scripts/adi_env.tcl
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source ../scripts/adi_ip_intel.tcl
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set_module_property NAME axi_dmac
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set_module_property DESCRIPTION "AXI DMA Controller"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME axi_dmac
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set_module_property ELABORATION_CALLBACK axi_dmac_elaborate
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set_module_property VALIDATION_CALLBACK axi_dmac_validate
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# files
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ad_ip_files axi_dmac [list \
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$ad_hdl_dir/library/util_cdc/sync_bits.v \
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$ad_hdl_dir/library/util_cdc/sync_event.v \
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$ad_hdl_dir/library/common/up_axi.v \
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$ad_hdl_dir/library/util_axis_fifo/util_axis_fifo.v \
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$ad_hdl_dir/library/util_axis_fifo/util_axis_fifo_address_generator.v \
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$ad_hdl_dir/library/common/ad_mem_asym.v \
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inc_id.vh \
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resp.vh \
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axi_dmac_burst_memory.v \
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axi_dmac_regmap.v \
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axi_dmac_regmap_request.v \
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axi_dmac_reset_manager.v \
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axi_dmac_resize_dest.v \
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axi_dmac_resize_src.v \
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axi_dmac_response_manager.v \
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axi_dmac_transfer.v \
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address_generator.v \
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data_mover.v \
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request_arb.v \
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request_generator.v \
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response_handler.v \
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axi_register_slice.v \
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dmac_2d_transfer.v \
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dest_axi_mm.v \
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dest_axi_stream.v \
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dest_fifo_inf.v \
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src_axi_mm.v \
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src_axi_stream.v \
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src_fifo_inf.v \
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splitter.v \
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response_generator.v \
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axi_dmac.v \
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axi_dmac_constr.sdc \
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]
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# Disable dual-clock RAM read-during-write behaviour warning.
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set_qip_strings { "set_instance_assignment -name MESSAGE_DISABLE 276027 -entity axi_dmac_burst_memory" }
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# parameters
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set group "General Configuration"
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add_parameter ID INTEGER 0
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set_parameter_property ID DISPLAY_NAME "Core ID"
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set_parameter_property ID HDL_PARAMETER true
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set_parameter_property ID GROUP $group
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add_parameter DMA_LENGTH_WIDTH INTEGER 24
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set_parameter_property DMA_LENGTH_WIDTH DISPLAY_NAME "DMA Transfer Length Register Width"
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set_parameter_property DMA_LENGTH_WIDTH UNITS Bits
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set_parameter_property DMA_LENGTH_WIDTH HDL_PARAMETER true
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set_parameter_property DMA_LENGTH_WIDTH ALLOWED_RANGES {8:32}
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set_parameter_property DMA_LENGTH_WIDTH GROUP $group
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add_parameter FIFO_SIZE INTEGER 8
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set_parameter_property FIFO_SIZE DISPLAY_NAME "Store-and-Forward Memory Size (In Bursts)"
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set_parameter_property FIFO_SIZE HDL_PARAMETER true
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set_parameter_property FIFO_SIZE ALLOWED_RANGES {2 4 8 16 32}
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set_parameter_property FIFO_SIZE GROUP $group
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add_parameter MAX_BYTES_PER_BURST INTEGER 128
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set_parameter_property MAX_BYTES_PER_BURST DISPLAY_NAME "Maximum bytes per burst"
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set_parameter_property MAX_BYTES_PER_BURST HDL_PARAMETER true
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set_parameter_property MAX_BYTES_PER_BURST GROUP $group
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foreach {suffix group} { \
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"SRC" "Source" \
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"DEST" "Destination" \
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} {
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add_display_item "Endpoint Configuration" $group "group"
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add_parameter DMA_TYPE_$suffix INTEGER 0
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set_parameter_property DMA_TYPE_$suffix DISPLAY_NAME "Type"
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set_parameter_property DMA_TYPE_$suffix HDL_PARAMETER true
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set_parameter_property DMA_TYPE_$suffix ALLOWED_RANGES \
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{ "0:Memory-Mapped AXI" "1:Streaming AXI" "2:FIFO Interface" }
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set_parameter_property DMA_TYPE_$suffix GROUP $group
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add_parameter DMA_AXI_PROTOCOL_$suffix INTEGER 1
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set_parameter_property DMA_AXI_PROTOCOL_$suffix DISPLAY_NAME "AXI Protocol"
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set_parameter_property DMA_AXI_PROTOCOL_$suffix HDL_PARAMETER true
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set_parameter_property DMA_AXI_PROTOCOL_$suffix ALLOWED_RANGES { "0:AXI4" "1:AXI3" }
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set_parameter_property DMA_AXI_PROTOCOL_$suffix GROUP $group
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add_parameter DMA_DATA_WIDTH_$suffix INTEGER 64
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set_parameter_property DMA_DATA_WIDTH_$suffix DISPLAY_NAME "Bus Width"
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set_parameter_property DMA_DATA_WIDTH_$suffix UNITS Bits
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set_parameter_property DMA_DATA_WIDTH_$suffix HDL_PARAMETER true
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set_parameter_property DMA_DATA_WIDTH_$suffix ALLOWED_RANGES {16 32 64 128 256 512 1024}
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set_parameter_property DMA_DATA_WIDTH_$suffix GROUP $group
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add_parameter AXI_SLICE_$suffix INTEGER 0
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set_parameter_property AXI_SLICE_$suffix DISPLAY_NAME "Insert Register Slice"
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set_parameter_property AXI_SLICE_$suffix DISPLAY_HINT boolean
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set_parameter_property AXI_SLICE_$suffix HDL_PARAMETER true
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set_parameter_property AXI_SLICE_$suffix GROUP $group
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}
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# FIFO interface
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set_parameter_property DMA_TYPE_SRC DEFAULT_VALUE 2
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set group "Features"
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add_parameter CYCLIC INTEGER 1
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set_parameter_property CYCLIC DISPLAY_NAME "Cyclic Transfer Support"
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set_parameter_property CYCLIC DISPLAY_HINT boolean
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set_parameter_property CYCLIC HDL_PARAMETER true
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set_parameter_property CYCLIC GROUP $group
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add_parameter DMA_2D_TRANSFER INTEGER 0
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set_parameter_property DMA_2D_TRANSFER DISPLAY_NAME "2D Transfer Support"
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set_parameter_property DMA_2D_TRANSFER DISPLAY_HINT boolean
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set_parameter_property DMA_2D_TRANSFER HDL_PARAMETER true
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set_parameter_property DMA_2D_TRANSFER GROUP $group
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add_parameter SYNC_TRANSFER_START INTEGER 0
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set_parameter_property SYNC_TRANSFER_START DISPLAY_NAME "Transfer Start Synchronization Support"
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set_parameter_property SYNC_TRANSFER_START DISPLAY_HINT boolean
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set_parameter_property SYNC_TRANSFER_START HDL_PARAMETER true
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set_parameter_property SYNC_TRANSFER_START GROUP $group
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set group "Clock Domain Configuration"
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add_parameter AUTO_ASYNC_CLK BOOLEAN 1
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set_parameter_property AUTO_ASYNC_CLK DISPLAY_NAME "Automatically Detect Clock Domains"
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set_parameter_property AUTO_ASYNC_CLK HDL_PARAMETER false
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set_parameter_property AUTO_ASYNC_CLK GROUP $group
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foreach {p name} { \
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ASYNC_CLK_REQ_SRC "Request and Source" \
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ASYNC_CLK_SRC_DEST "Source and Destination" \
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ASYNC_CLK_DEST_REQ "Destination and Request" \
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} {
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add_parameter ${p}_MANUAL INTEGER 1
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set_parameter_property ${p}_MANUAL DISPLAY_NAME [concat $name "Clock Asynchronous"]
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set_parameter_property ${p}_MANUAL DISPLAY_HINT boolean
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set_parameter_property ${p}_MANUAL HDL_PARAMETER false
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set_parameter_property ${p}_MANUAL VISIBLE false
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set_parameter_property ${p}_MANUAL GROUP $group
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add_parameter $p INTEGER 1
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set_parameter_property $p DISPLAY_NAME [concat $name "Clock Asynchronous"]
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set_parameter_property $p DISPLAY_HINT boolean
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set_parameter_property $p HDL_PARAMETER true
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set_parameter_property $p DERIVED true
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set_parameter_property $p GROUP $group
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}
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add_parameter CLK_DOMAIN_REQ INTEGER
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set_parameter_property CLK_DOMAIN_REQ HDL_PARAMETER false
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set_parameter_property CLK_DOMAIN_REQ SYSTEM_INFO {CLOCK_DOMAIN s_axi_clock}
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set_parameter_property CLK_DOMAIN_REQ VISIBLE false
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set_parameter_property CLK_DOMAIN_REQ GROUP $group
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set src_clks { \
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{CLK_DOMAIN_SRC_AXI m_src_axi_clock} \
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{CLK_DOMAIN_SRC_SAXI if_s_axis_aclk} \
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{CLK_DOMAIN_SRC_FIFO if_fifo_wr_clk} \
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}
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set dest_clks { \
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{CLK_DOMAIN_DEST_AXI m_dest_axi_clock} \
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{CLK_DOMAIN_DEST_SAXI if_m_axis_aclk} \
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{CLK_DOMAIN_DEST_FIFO if_fifo_rd_clk} \
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}
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foreach domain [list {*}$src_clks {*}$dest_clks] {
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lassign $domain p clk
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add_parameter $p INTEGER
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set_parameter_property $p HDL_PARAMETER false
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set_parameter_property $p SYSTEM_INFO [list CLOCK_DOMAIN $clk]
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set_parameter_property $p VISIBLE false
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set_parameter_property $p GROUP $group
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}
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# axi4 slave
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ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 11
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add_interface interrupt_sender interrupt end
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set_interface_property interrupt_sender associatedAddressablePoint s_axi
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set_interface_property interrupt_sender associatedClock s_axi_clock
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set_interface_property interrupt_sender associatedReset s_axi_reset
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set_interface_property interrupt_sender ENABLED true
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set_interface_property interrupt_sender EXPORT_OF ""
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set_interface_property interrupt_sender PORT_NAME_MAP ""
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set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
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set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
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add_interface_port interrupt_sender irq irq Output 1
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proc axi_dmac_validate {} {
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set auto_clk [get_parameter_value AUTO_ASYNC_CLK]
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set type_src [get_parameter_value DMA_TYPE_SRC]
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set type_dest [get_parameter_value DMA_TYPE_DEST]
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set max_burst 32768
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if {$auto_clk == true} {
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global src_clks dest_clks
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set req_domain [get_parameter_value CLK_DOMAIN_REQ]
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set src_domain [get_parameter_value [lindex $src_clks $type_src 0]]
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set dest_domain [get_parameter_value [lindex $dest_clks $type_dest 0]]
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if {$req_domain != 0 && $req_domain == $src_domain} {
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set_parameter_value ASYNC_CLK_REQ_SRC 0
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} else {
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set_parameter_value ASYNC_CLK_REQ_SRC 1
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}
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if {$src_domain != 0 && $src_domain == $dest_domain} {
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set_parameter_value ASYNC_CLK_SRC_DEST 0
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} else {
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set_parameter_value ASYNC_CLK_SRC_DEST 1
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}
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if {$dest_domain != 0 && $dest_domain == $req_domain} {
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set_parameter_value ASYNC_CLK_DEST_REQ 0
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} else {
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set_parameter_value ASYNC_CLK_DEST_REQ 1
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}
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} else {
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foreach p {ASYNC_CLK_REQ_SRC ASYNC_CLK_SRC_DEST ASYNC_CLK_DEST_REQ} {
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set_parameter_value $p [get_parameter_value ${p}_MANUAL]
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}
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}
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foreach p {ASYNC_CLK_REQ_SRC ASYNC_CLK_SRC_DEST ASYNC_CLK_DEST_REQ} {
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set_parameter_property ${p}_MANUAL VISIBLE [expr $auto_clk ? false : true]
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set_parameter_property $p VISIBLE $auto_clk
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}
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foreach suffix {SRC DEST} {
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if {[get_parameter_value DMA_TYPE_$suffix] == 0} {
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set show_axi_protocol true
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set proto [get_parameter_value DMA_AXI_PROTOCOL_$suffix]
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set width [get_parameter_value DMA_DATA_WIDTH_$suffix]
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if {$proto == 0} {
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set max_burst [expr min($max_burst, $width * 256 / 8)]
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} else {
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set max_burst [expr min($max_burst, $width * 16 / 8)]
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}
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} else {
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set show_axi_protocol false
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}
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set_parameter_property DMA_AXI_PROTOCOL_$suffix VISIBLE $show_axi_protocol
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}
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set_parameter_property MAX_BYTES_PER_BURST ALLOWED_RANGES "1:$max_burst"
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}
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# conditional interfaces
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# axi4 destination/source
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add_interface m_dest_axi_clock clock end
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add_interface_port m_dest_axi_clock m_dest_axi_aclk clk Input 1
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add_interface m_dest_axi_reset reset end
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set_interface_property m_dest_axi_reset associatedClock m_dest_axi_clock
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add_interface_port m_dest_axi_reset m_dest_axi_aresetn reset_n Input 1
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add_interface m_src_axi_clock clock end
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add_interface_port m_src_axi_clock m_src_axi_aclk clk Input 1
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add_interface m_src_axi_reset reset end
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set_interface_property m_src_axi_reset associatedClock m_src_axi_clock
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add_interface_port m_src_axi_reset m_src_axi_aresetn reset_n Input 1
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# axis destination/source
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ad_interface clock m_axis_aclk input 1 clk
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ad_interface signal m_axis_xfer_req output 1 xfer_req
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add_interface m_axis axi4stream start
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set_interface_property m_axis associatedClock if_m_axis_aclk
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set_interface_property m_axis associatedReset s_axi_reset
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add_interface_port m_axis m_axis_valid tvalid Output 1
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add_interface_port m_axis m_axis_last tlast Output 1
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add_interface_port m_axis m_axis_ready tready Input 1
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add_interface_port m_axis m_axis_data tdata Output DMA_DATA_WIDTH_DEST
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add_interface_port m_axis m_axis_user tuser Output 1
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add_interface_port m_axis m_axis_id tid Output DMA_AXIS_ID_W
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add_interface_port m_axis m_axis_dest tdest Output DMA_AXIS_DEST_W
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add_interface_port m_axis m_axis_strb tstrb Output DMA_DATA_WIDTH_DEST/8
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add_interface_port m_axis m_axis_keep tkeep Output DMA_DATA_WIDTH_DEST/8
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ad_interface clock s_axis_aclk input 1 clk
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ad_interface signal s_axis_xfer_req output 1 xfer_req
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add_interface s_axis axi4stream end
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set_interface_property s_axis associatedClock if_s_axis_aclk
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set_interface_property s_axis associatedReset s_axi_reset
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add_interface_port s_axis s_axis_valid tvalid Input 1
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add_interface_port s_axis s_axis_last tlast Input 1
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add_interface_port s_axis s_axis_ready tready Output 1
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add_interface_port s_axis s_axis_data tdata Input DMA_DATA_WIDTH_SRC
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add_interface_port s_axis s_axis_user tuser Input 1
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add_interface_port s_axis s_axis_id tid Input DMA_AXIS_ID_W
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add_interface_port s_axis s_axis_dest tdest Input DMA_AXIS_DEST_W
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add_interface_port s_axis s_axis_strb tstrb Input DMA_DATA_WIDTH_SRC/8
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add_interface_port s_axis s_axis_keep tkeep Input DMA_DATA_WIDTH_SRC/8
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# fifo destination/source
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ad_interface clock fifo_rd_clk input 1 clk
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ad_interface signal fifo_rd_en input 1 valid
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ad_interface signal fifo_rd_valid output 1 valid
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ad_interface signal fifo_rd_dout output DMA_DATA_WIDTH_DEST data
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ad_interface signal fifo_rd_underflow output 1 unf
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ad_interface signal fifo_rd_xfer_req output 1 xfer_req
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ad_interface clock fifo_wr_clk input 1 clk
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ad_interface signal fifo_wr_en input 1 valid
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ad_interface signal fifo_wr_din input DMA_DATA_WIDTH_SRC data
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ad_interface signal fifo_wr_overflow output 1 ovf
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ad_interface signal fifo_wr_sync input 1 sync
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ad_interface signal fifo_wr_xfer_req output 1 xfer_req
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proc add_axi_master_interface {axi_type port suffix} {
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add_interface $port $axi_type start
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set_interface_property $port associatedClock ${port}_clock
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set_interface_property $port associatedReset ${port}_reset
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set_interface_property $port readIssuingCapability 1
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add_interface_port $port ${port}_awvalid awvalid Output 1
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add_interface_port $port ${port}_awaddr awaddr Output 32
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add_interface_port $port ${port}_awready awready Input 1
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add_interface_port $port ${port}_wvalid wvalid Output 1
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add_interface_port $port ${port}_wdata wdata Output DMA_DATA_WIDTH_${suffix}
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add_interface_port $port ${port}_wstrb wstrb Output DMA_DATA_WIDTH_${suffix}/8
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add_interface_port $port ${port}_wready wready Input 1
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add_interface_port $port ${port}_bvalid bvalid Input 1
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add_interface_port $port ${port}_bresp bresp Input 2
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add_interface_port $port ${port}_bready bready Output 1
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add_interface_port $port ${port}_arvalid arvalid Output 1
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add_interface_port $port ${port}_araddr araddr Output 32
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add_interface_port $port ${port}_arready arready Input 1
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add_interface_port $port ${port}_rvalid rvalid Input 1
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add_interface_port $port ${port}_rresp rresp Input 2
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add_interface_port $port ${port}_rdata rdata Input DMA_DATA_WIDTH_${suffix}
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add_interface_port $port ${port}_rready rready Output 1
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add_interface_port $port ${port}_awlen awlen Output "8-(4*DMA_AXI_PROTOCOL_${suffix})"
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add_interface_port $port ${port}_awsize awsize Output 3
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add_interface_port $port ${port}_awburst awburst Output 2
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add_interface_port $port ${port}_awcache awcache Output 4
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add_interface_port $port ${port}_awprot awprot Output 3
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add_interface_port $port ${port}_wlast wlast Output 1
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add_interface_port $port ${port}_arlen arlen Output "8-(4*DMA_AXI_PROTOCOL_${suffix})"
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add_interface_port $port ${port}_arsize arsize Output 3
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add_interface_port $port ${port}_arburst arburst Output 2
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add_interface_port $port ${port}_arcache arcache Output 4
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add_interface_port $port ${port}_arprot arprot Output 3
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# Some signals are mandatory in Intel's implementation of AXI3
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# awid, awlock, wid, bid, arid, arlock, rid, rlast
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# Hide them in AXI4
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add_interface_port $port ${port}_awid awid Output 1
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add_interface_port $port ${port}_awlock awlock Output "1+DMA_AXI_PROTOCOL_${suffix}"
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add_interface_port $port ${port}_wid wid Output 1
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add_interface_port $port ${port}_arid arid Output 1
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add_interface_port $port ${port}_arlock arlock Output "1+DMA_AXI_PROTOCOL_${suffix}"
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add_interface_port $port ${port}_rid rid Input 1
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add_interface_port $port ${port}_bid bid Input 1
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add_interface_port $port ${port}_rlast rlast Input 1
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if {$axi_type == "axi4"} {
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set_port_property ${port}_awid TERMINATION true
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set_port_property ${port}_awlock TERMINATION true
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set_port_property ${port}_wid TERMINATION true
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set_port_property ${port}_arid TERMINATION true
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set_port_property ${port}_arlock TERMINATION true
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set_port_property ${port}_rid TERMINATION true
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set_port_property ${port}_bid TERMINATION true
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if {$port == "m_dest_axi"} {
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set_port_property ${port}_rlast TERMINATION true
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}
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}
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}
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proc axi_dmac_elaborate {} {
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set fifo_size [get_parameter_value FIFO_SIZE]
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set disabled_intfs {}
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# add axi3 or axi4 interface depending on user selection
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foreach {suffix port} {SRC m_src_axi DEST m_dest_axi} {
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if {[get_parameter_value DMA_AXI_PROTOCOL_${suffix}] == 0} {
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set axi_type axi4
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} else {
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set axi_type axi
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}
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add_axi_master_interface $axi_type $port $suffix
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}
|
|
|
|
# axi4 destination/source
|
|
|
|
if {[get_parameter_value DMA_TYPE_DEST] == 0} {
|
|
set_interface_property m_dest_axi writeIssuingCapability $fifo_size
|
|
set_interface_property m_dest_axi combinedIssuingCapability $fifo_size
|
|
} else {
|
|
lappend disabled_intfs m_dest_axi_clock m_dest_axi_reset m_dest_axi
|
|
}
|
|
|
|
if {[get_parameter_value DMA_TYPE_SRC] == 0} {
|
|
set_interface_property m_src_axi readIssuingCapability $fifo_size
|
|
set_interface_property m_src_axi combinedIssuingCapability $fifo_size
|
|
} else {
|
|
lappend disabled_intfs m_src_axi_clock m_src_axi_reset m_src_axi
|
|
}
|
|
|
|
# axis destination/source
|
|
|
|
if {[get_parameter_value DMA_TYPE_DEST] != 1} {
|
|
lappend disabled_intfs if_m_axis_aclk if_m_axis_xfer_req m_axis
|
|
} else {
|
|
if {[get_parameter_value HAS_AXIS_TSTRB] == 0} {
|
|
set_port_property m_axis_strb termination true
|
|
}
|
|
if {[get_parameter_value HAS_AXIS_TKEEP] == 0} {
|
|
set_port_property m_axis_keep termination true
|
|
}
|
|
if {[get_parameter_value HAS_AXIS_TLAST] == 0} {
|
|
set_port_property m_axis_last termination true
|
|
}
|
|
if {[get_parameter_value HAS_AXIS_TID] == 0} {
|
|
set_port_property m_axis_id termination true
|
|
}
|
|
if {[get_parameter_value HAS_AXIS_TDEST] == 0} {
|
|
set_port_property m_axis_dest termination true
|
|
}
|
|
if {[get_parameter_value HAS_AXIS_TUSER] == 0} {
|
|
set_port_property m_axis_user termination true
|
|
}
|
|
}
|
|
|
|
if {[get_parameter_value DMA_TYPE_SRC] != 1} {
|
|
lappend disabled_intfs if_s_axis_aclk if_s_axis_xfer_req s_axis
|
|
} else {
|
|
if {[get_parameter_value HAS_AXIS_TSTRB] == 0} {
|
|
set_port_property s_axis_strb termination true
|
|
set_port_property s_axis_strb termination_value 0xFF
|
|
}
|
|
if {[get_parameter_value HAS_AXIS_TKEEP] == 0} {
|
|
set_port_property s_axis_keep termination true
|
|
set_port_property s_axis_keep termination_value 0xFF
|
|
}
|
|
if {[get_parameter_value HAS_AXIS_TLAST] == 0} {
|
|
set_port_property s_axis_last termination true
|
|
set_port_property s_axis_last termination_value 0
|
|
}
|
|
if {[get_parameter_value HAS_AXIS_TID] == 0} {
|
|
set_port_property s_axis_id termination true
|
|
set_port_property s_axis_id termination_value 0
|
|
}
|
|
if {[get_parameter_value HAS_AXIS_TDEST] == 0} {
|
|
set_port_property s_axis_dest termination true
|
|
set_port_property s_axis_dest termination_value 0
|
|
}
|
|
if {[get_parameter_value HAS_AXIS_TUSER] == 0} {
|
|
if {[get_parameter_value SYNC_TRANSFER_START] == 0} {
|
|
set_port_property s_axis_user termination true
|
|
set_port_property s_axis_user termination_value 0
|
|
}
|
|
}
|
|
}
|
|
|
|
# fifo destination/source
|
|
|
|
if {[get_parameter_value DMA_TYPE_DEST] != 2} {
|
|
lappend disabled_intfs \
|
|
if_fifo_rd_clk if_fifo_rd_en if_fifo_rd_valid if_fifo_rd_dout \
|
|
if_fifo_rd_underflow if_fifo_rd_xfer_req
|
|
}
|
|
|
|
if {[get_parameter_value DMA_TYPE_SRC] != 2} {
|
|
lappend disabled_intfs \
|
|
if_fifo_wr_clk if_fifo_wr_en if_fifo_wr_din if_fifo_wr_overflow \
|
|
if_fifo_wr_sync if_fifo_wr_xfer_req
|
|
}
|
|
|
|
if {[get_parameter_value DMA_TYPE_SRC] == 2 &&
|
|
[get_parameter_value SYNC_TRANSFER_START] == 0} {
|
|
set_port_property fifo_wr_sync termination true
|
|
set_port_property fifo_wr_sync termination_value 1
|
|
}
|
|
|
|
if {[get_parameter_value ENABLE_DIAGNOSTICS_IF] != 1} {
|
|
lappend disabled_intfs diagnostics_if
|
|
}
|
|
|
|
foreach intf $disabled_intfs {
|
|
set_interface_property $intf ENABLED false
|
|
}
|
|
}
|
|
|
|
set group "Debug"
|
|
|
|
add_parameter DISABLE_DEBUG_REGISTERS INTEGER 0
|
|
set_parameter_property DISABLE_DEBUG_REGISTERS DISPLAY_NAME "Disable debug registers"
|
|
set_parameter_property DISABLE_DEBUG_REGISTERS DISPLAY_HINT boolean
|
|
set_parameter_property DISABLE_DEBUG_REGISTERS HDL_PARAMETER false
|
|
set_parameter_property DISABLE_DEBUG_REGISTERS GROUP $group
|
|
|
|
add_parameter ENABLE_DIAGNOSTICS_IF INTEGER 0
|
|
set_parameter_property ENABLE_DIAGNOSTICS_IF DISPLAY_NAME "Enable Diagnostics Interface"
|
|
set_parameter_property ENABLE_DIAGNOSTICS_IF DISPLAY_HINT boolean
|
|
set_parameter_property ENABLE_DIAGNOSTICS_IF HDL_PARAMETER true
|
|
set_parameter_property ENABLE_DIAGNOSTICS_IF GROUP $group
|
|
|
|
add_interface diagnostics_if conduit end
|
|
add_interface_port diagnostics_if dest_diag_level_bursts dest_diag_level_bursts Output "8"
|
|
|
|
set group "AXI Stream interface common configuration"
|
|
|
|
add_parameter HAS_AXIS_TSTRB INTEGER 0
|
|
set_parameter_property HAS_AXIS_TSTRB DISPLAY_NAME "AXI Stream interface has TSTRB"
|
|
set_parameter_property HAS_AXIS_TSTRB DISPLAY_HINT boolean
|
|
set_parameter_property HAS_AXIS_TSTRB HDL_PARAMETER false
|
|
set_parameter_property HAS_AXIS_TSTRB GROUP $group
|
|
|
|
add_parameter HAS_AXIS_TKEEP INTEGER 0
|
|
set_parameter_property HAS_AXIS_TKEEP DISPLAY_NAME "AXI Stream interface has TKEEP"
|
|
set_parameter_property HAS_AXIS_TKEEP DISPLAY_HINT boolean
|
|
set_parameter_property HAS_AXIS_TKEEP HDL_PARAMETER false
|
|
set_parameter_property HAS_AXIS_TKEEP GROUP $group
|
|
|
|
add_parameter HAS_AXIS_TLAST INTEGER 0
|
|
set_parameter_property HAS_AXIS_TLAST DISPLAY_NAME "AXI Stream interface has TLAST"
|
|
set_parameter_property HAS_AXIS_TLAST DISPLAY_HINT boolean
|
|
set_parameter_property HAS_AXIS_TLAST HDL_PARAMETER false
|
|
set_parameter_property HAS_AXIS_TLAST GROUP $group
|
|
|
|
add_parameter HAS_AXIS_TID INTEGER 0
|
|
set_parameter_property HAS_AXIS_TID DISPLAY_NAME "AXI Stream interface has TID"
|
|
set_parameter_property HAS_AXIS_TID DISPLAY_HINT boolean
|
|
set_parameter_property HAS_AXIS_TID HDL_PARAMETER false
|
|
set_parameter_property HAS_AXIS_TID GROUP $group
|
|
|
|
add_parameter DMA_AXIS_ID_W INTEGER 8
|
|
set_parameter_property DMA_AXIS_ID_W DISPLAY_NAME "AXI Stream TID width"
|
|
set_parameter_property DMA_AXIS_ID_W HDL_PARAMETER true
|
|
set_parameter_property DMA_AXIS_ID_W GROUP $group
|
|
|
|
add_parameter HAS_AXIS_TDEST INTEGER 0
|
|
set_parameter_property HAS_AXIS_TDEST DISPLAY_NAME "AXI Stream interface has TDEST"
|
|
set_parameter_property HAS_AXIS_TDEST DISPLAY_HINT boolean
|
|
set_parameter_property HAS_AXIS_TDEST HDL_PARAMETER false
|
|
set_parameter_property HAS_AXIS_TDEST GROUP $group
|
|
|
|
add_parameter DMA_AXIS_DEST_W INTEGER 4
|
|
set_parameter_property DMA_AXIS_DEST_W DISPLAY_NAME "AXI Stream TDEST width"
|
|
set_parameter_property DMA_AXIS_DEST_W HDL_PARAMETER true
|
|
set_parameter_property DMA_AXIS_DEST_W GROUP $group
|
|
|
|
add_parameter HAS_AXIS_TUSER INTEGER 0
|
|
set_parameter_property HAS_AXIS_TUSER DISPLAY_NAME "AXI Stream interface has TUSER"
|
|
set_parameter_property HAS_AXIS_TUSER DISPLAY_HINT boolean
|
|
set_parameter_property HAS_AXIS_TUSER HDL_PARAMETER false
|
|
set_parameter_property HAS_AXIS_TUSER GROUP $group
|