zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
4,026 Commits
1 Branch
0 Tags
23 MiB
Verilog 61.7%
Tcl 31.2%
Makefile 3.5%
VHDL 1.9%
SystemVerilog 1%
Other 0.6%
 
 
 
 
 
 
Go to file
Lars-Peter Clausen d164209355 jesd204: axi_jesd204_up_rx_lane: Fix padding signal width 
The upper padding zeros should be 26 bits wide.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2017-07-17 17:13:02 +02:00
library jesd204: axi_jesd204_up_rx_lane: Fix padding signal width 2017-07-17 17:13:02 +02:00
projects adrv9371x: Write parameter as hexa value to clear Vivados ambiguity between decimal and binary 2017-07-14 10:20:57 +03:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore Update .gitignore 2016-12-19 15:37:05 +00:00
LICENSE license: GPL must be GPL v2 2017-05-31 18:18:45 +03:00
LICENSE_ADIBSD license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_GPL2 license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_LGPL license: Add top level license files 2017-05-29 09:57:39 +03:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update the README 2016-03-31 19:42:52 +03:00

README.md

HDL Reference Designs

Analog Devices Inc. HDL libraries and projects

Branches

Each release has its own branch and master always synced with the latest release. To find out more information about the latest release please check the release notes. Every branch, which has dev in its name, is a development branch and should handle it accordingly.

Latest Release Notes

HDL User Guide

HDL Help & Support