354 lines
13 KiB
Verilog
354 lines
13 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dacfifo_dac #(
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parameter AXI_DATA_WIDTH = 512,
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parameter AXI_LENGTH = 15,
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parameter DAC_DATA_WIDTH = 64,
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parameter DAC_MEM_ADDRESS_WIDTH = 8) (
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input axi_clk,
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input axi_dvalid,
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input [(AXI_DATA_WIDTH-1):0] axi_ddata,
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output reg axi_dready,
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input axi_dlast,
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input axi_xfer_req,
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input [ 3:0] dma_last_beats,
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input dac_clk,
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input dac_rst,
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input dac_valid,
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output [(DAC_DATA_WIDTH-1):0] dac_data,
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output dac_xfer_out,
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output reg dac_dunf);
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localparam MEM_RATIO = AXI_DATA_WIDTH/DAC_DATA_WIDTH;
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localparam AXI_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_MEM_ADDRESS_WIDTH :
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(MEM_RATIO == 2) ? (DAC_MEM_ADDRESS_WIDTH - 1) :
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(MEM_RATIO == 4) ? (DAC_MEM_ADDRESS_WIDTH - 2) :
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(DAC_MEM_ADDRESS_WIDTH - 3);
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localparam AXI_BUF_THRESHOLD_LO = 3 * (AXI_LENGTH+1);
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localparam AXI_BUF_THRESHOLD_HI = {(AXI_ADDRESS_WIDTH){1'b1}} - (AXI_LENGTH+1);
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localparam DAC_BUF_THRESHOLD_LO = 3 * (AXI_LENGTH+1) * MEM_RATIO;
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localparam DAC_BUF_THRESHOLD_HI = {(DAC_MEM_ADDRESS_WIDTH){1'b1}} - (AXI_LENGTH+1) * MEM_RATIO;
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localparam DAC_ARINCR = (AXI_LENGTH+1) * MEM_RATIO;
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// internal registers
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reg [(AXI_ADDRESS_WIDTH-1):0] axi_mem_waddr = 'd0;
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reg [(AXI_ADDRESS_WIDTH-1):0] axi_mem_laddr = 'd0;
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reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_g = 'd0;
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reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr_g = 'd0;
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reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr = 'd0;
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reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m1 = 'd0;
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reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m2 = 'd0;
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reg [(AXI_ADDRESS_WIDTH-1):0] axi_mem_addr_diff = 'd0;
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reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_raddr = 'd0;
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reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_raddr_g = 'd0;
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reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr = 'd0;
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reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr_m1 = 'd0;
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reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2 = 'd0;
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reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_laddr = 'd0;
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reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_laddr_m1 = 'd0;
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reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_laddr_m2 = 'd0;
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reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_addr_diff = 'd0;
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reg dac_mem_init = 1'b0;
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reg dac_mem_init_d = 1'b0;
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reg dac_mem_enable = 1'b0;
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reg [ 2:0] dac_xfer_req_m = 3'b0;
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reg dac_xfer_init = 1'b0;
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reg [ 3:0] dac_last_beats = 4'b0;
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reg [ 3:0] dac_last_beats_m = 4'b0;
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reg [ 3:0] dac_beat_cnt = 4'b0;
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reg dac_dlast = 1'b0;
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reg dac_dlast_m1 = 1'b0;
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reg dac_dlast_m2 = 1'b0;
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reg dac_dlast_inmem = 1'b0;
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reg dac_mem_valid = 1'b0;
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// internal signals
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wire [AXI_ADDRESS_WIDTH:0] axi_mem_addr_diff_s;
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wire [(AXI_ADDRESS_WIDTH-1):0] axi_mem_raddr_s;
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wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_s;
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wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr_s;
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wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_b2g_s;
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wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr_b2g_s;
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wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m2_g2b_s;
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wire [DAC_MEM_ADDRESS_WIDTH:0] dac_mem_addr_diff_s;
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wire dac_xfer_init_s;
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wire dac_last_axi_beats_s;
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wire [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_raddr_b2g_s;
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wire [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2_g2b_s;
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wire [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_laddr_m2_g2b_s;
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// write interface
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always @(posedge axi_clk) begin
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if (axi_xfer_req == 1'b0) begin
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axi_mem_waddr <= 'd0;
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axi_mem_waddr_g <= 'd0;
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axi_mem_laddr <= {AXI_ADDRESS_WIDTH{1'b1}};
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end else begin
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if (axi_dvalid == 1'b1) begin
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axi_mem_waddr <= axi_mem_waddr + 1'b1;
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axi_mem_laddr <= (axi_dlast == 1'b1) ? axi_mem_waddr : axi_mem_laddr;
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end
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axi_mem_waddr_g <= axi_mem_waddr_b2g_s;
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axi_mem_laddr_g <= axi_mem_laddr_b2g_s;
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end
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end
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ad_b2g # (
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.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
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) i_axi_mem_waddr_b2g (
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.din (axi_mem_waddr_s),
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.dout (axi_mem_waddr_b2g_s));
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ad_b2g # (
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.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
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) i_axi_mem_laddr_b2g (
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.din (axi_mem_laddr_s),
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.dout (axi_mem_laddr_b2g_s));
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// scale the axi_mem_* addresses
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assign axi_mem_raddr_s = (MEM_RATIO == 1) ? axi_mem_raddr :
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(MEM_RATIO == 2) ? axi_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):1] :
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(MEM_RATIO == 4) ? axi_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):2] :
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axi_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):3];
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assign axi_mem_waddr_s = (MEM_RATIO == 1) ? axi_mem_waddr :
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(MEM_RATIO == 2) ? {axi_mem_waddr, 1'b0} :
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(MEM_RATIO == 4) ? {axi_mem_waddr, 2'b0} :
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{axi_mem_waddr, 3'b0};
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assign axi_mem_laddr_s = (MEM_RATIO == 1) ? axi_mem_laddr :
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(MEM_RATIO == 2) ? {axi_mem_laddr, 1'b0} :
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(MEM_RATIO == 4) ? {axi_mem_laddr, 2'b0} :
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{axi_mem_laddr, 3'b0};
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// incomming data flow control
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assign axi_mem_addr_diff_s = {1'b1, axi_mem_waddr} - axi_mem_raddr_s;
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always @(posedge axi_clk) begin
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if (axi_xfer_req == 1'b0) begin
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axi_mem_addr_diff <= 'd0;
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axi_mem_raddr <= 'd0;
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axi_mem_raddr_m1 <= 'd0;
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axi_mem_raddr_m2 <= 'd0;
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axi_dready <= 'd0;
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end else begin
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axi_mem_raddr_m1 <= dac_mem_raddr_g;
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axi_mem_raddr_m2 <= axi_mem_raddr_m1;
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axi_mem_raddr <= axi_mem_raddr_m2_g2b_s;
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axi_mem_addr_diff <= axi_mem_addr_diff_s[AXI_ADDRESS_WIDTH-1:0];
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if (axi_mem_addr_diff >= AXI_BUF_THRESHOLD_HI) begin
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axi_dready <= 1'b0;
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end else begin
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axi_dready <= 1'b1;
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end
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end
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end
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ad_g2b #(
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.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
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) i_axi_mem_raddr_m2_g2b (
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.din (axi_mem_raddr_m2),
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.dout (axi_mem_raddr_m2_g2b_s));
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// CDC for xfer_req signal
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always @(posedge dac_clk) begin
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if (dac_rst == 1'b1) begin
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dac_xfer_req_m <= 3'b0;
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end else begin
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dac_xfer_req_m <= {dac_xfer_req_m[1:0], axi_xfer_req};
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end
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end
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assign dac_xfer_out = dac_xfer_req_m[2];
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assign dac_xfer_init_s = ~dac_xfer_req_m[2] & dac_xfer_req_m[1];
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// read interface
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always @(posedge dac_clk) begin
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if (dac_xfer_out == 1'b0) begin
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dac_mem_init <= 1'b0;
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dac_mem_init_d <= 1'b0;
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dac_mem_enable <= 1'b0;
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end else begin
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if (dac_xfer_init == 1'b1) begin
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dac_mem_init <= 1'b1;
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end
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if ((dac_mem_init == 1'b1) && (dac_mem_addr_diff > DAC_BUF_THRESHOLD_LO)) begin
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dac_mem_init <= 1'b0;
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end
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dac_mem_init_d <= dac_mem_init;
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// memory is ready when the initial fill up is done
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dac_mem_enable <= (dac_mem_init_d & ~dac_mem_init) ? 1'b1 : dac_mem_enable;
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end
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dac_xfer_init <= dac_xfer_init_s;
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end
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always @(posedge dac_clk) begin
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if (dac_xfer_out == 1'b0) begin
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dac_mem_waddr <= 'b0;
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dac_mem_waddr_m1 <= 'b0;
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dac_mem_waddr_m2 <= 'b0;
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dac_mem_laddr <= 'b0;
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dac_mem_laddr_m1 <= 'b0;
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dac_mem_laddr_m2 <= 'b0;
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dac_dlast <= 1'b0;
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dac_dlast_m1 <= 1'b0;
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dac_dlast_m2 <= 1'b0;
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end else begin
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dac_mem_waddr_m1 <= axi_mem_waddr_g;
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dac_mem_waddr_m2 <= dac_mem_waddr_m1;
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dac_mem_waddr <= dac_mem_waddr_m2_g2b_s;
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dac_mem_laddr_m1 <= axi_mem_laddr_g;
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dac_mem_laddr_m2 <= dac_mem_laddr_m1;
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dac_mem_laddr <= dac_mem_laddr_m2_g2b_s;
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dac_dlast_m1 <= axi_dlast;
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dac_dlast_m2 <= dac_dlast_m1;
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dac_dlast <= dac_dlast_m2;
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end
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end
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ad_g2b #(
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.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
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) i_dac_mem_waddr_m2_g2b (
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.din (dac_mem_waddr_m2),
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.dout (dac_mem_waddr_m2_g2b_s));
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ad_g2b #(
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.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
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) i_dac_mem_laddr_m2_g2b (
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.din (dac_mem_laddr_m2),
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.dout (dac_mem_laddr_m2_g2b_s));
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assign dac_mem_addr_diff_s = {1'b1, dac_mem_waddr} - dac_mem_raddr;
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always @(posedge dac_clk) begin
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dac_mem_valid <= (dac_mem_enable) ? dac_valid : 1'b0;
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end
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// CDC for the dma_last_beats
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always @(posedge dac_clk) begin
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if (dac_rst == 1'b1) begin
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dac_last_beats <= 4'b0;
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dac_last_beats_m <= 4'b0;
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end else begin
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dac_last_beats_m <= dma_last_beats;
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dac_last_beats <= dac_last_beats_m;
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end
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end
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// If the MEM_RATIO is grater than one, it can happen that not all the DAC beats from
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// an AXI beat are valid. In this case the invalid data is dropped.
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// The axi_dlast indicates the last AXI beat. The valid number of DAC beats on the last AXI beat
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// commes from the AXI write module. (axi_dacfifo_wr.v)
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assign dac_last_axi_beats_s = ((dac_dlast_inmem == 1'b1) && (dac_mem_raddr >= dac_mem_laddr) && (dac_mem_raddr < dac_mem_laddr + MEM_RATIO)) ? 1'b1 : 1'b0;
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always @(posedge dac_clk) begin
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if (dac_xfer_out == 1'b0) begin
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dac_mem_raddr <= 'd0;
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dac_beat_cnt <= 'd0;
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dac_dlast_inmem <= 1'b0;
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end else begin
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if (dac_dlast == 1'b1) begin
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dac_dlast_inmem <= 1'b1;
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end else if (dac_mem_raddr == dac_mem_laddr + MEM_RATIO) begin
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dac_dlast_inmem <= 1'b0;
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end
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if (dac_mem_valid == 1'b1) begin
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dac_beat_cnt <= ((dac_beat_cnt >= MEM_RATIO-1) ||
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((dac_last_beats > 4'b1) && (dac_last_axi_beats_s > 1'b0) && (dac_beat_cnt == dac_last_beats-1))) ? 0 : dac_beat_cnt + 1;
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dac_mem_raddr <= ((dac_last_axi_beats_s) && (dac_beat_cnt == dac_last_beats-1)) ? (dac_mem_laddr + MEM_RATIO) : dac_mem_raddr + 1'b1;
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end
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dac_mem_raddr_g <= dac_mem_raddr_b2g_s;
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end
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end
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ad_b2g # (
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.DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH)
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) i_dac_mem_raddr_b2g (
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.din (dac_mem_raddr),
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.dout (dac_mem_raddr_b2g_s));
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// underflow generation, there is no overflow
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always @(posedge dac_clk) begin
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if(dac_xfer_out == 1'b0) begin
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dac_mem_addr_diff <= 'b0;
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dac_dunf <= 1'b0;
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end else begin
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dac_mem_addr_diff <= dac_mem_addr_diff_s[DAC_MEM_ADDRESS_WIDTH-1:0];
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dac_dunf <= (dac_mem_addr_diff == 1'b0) ? 1'b1 : 1'b0;
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end
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end
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// instantiations
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ad_mem_asym #(
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.A_ADDRESS_WIDTH (AXI_ADDRESS_WIDTH),
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.A_DATA_WIDTH (AXI_DATA_WIDTH),
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.B_ADDRESS_WIDTH (DAC_MEM_ADDRESS_WIDTH),
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.B_DATA_WIDTH (DAC_DATA_WIDTH))
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i_mem_asym (
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.clka (axi_clk),
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.wea (axi_dvalid),
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.addra (axi_mem_waddr),
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.dina (axi_ddata),
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.clkb (dac_clk),
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.addrb (dac_mem_raddr),
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.doutb (dac_data));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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