e4c9c8734c
For most of the DACs that use JESD204 as the data transport the digital interface is very similar. They are mainly differentiated by number of JESD204 lanes, number of converter channels and number of bits per sample. Currently for each supported converter there exists a converter specific core which has the converter specific requirements hard-coded. Introduce a new generic core that has the number of lanes, number of channels and bits per sample as synthesis-time configurable parameters. It can be used as a drop-in replacement for the existing converter specific cores. This has the advantage of a shared and reduced code base. Code improvements will automatically be available for all converters and don't have to be manually ported to each core individually. It also makes it very easy to introduce support for new converters that follow the existing schema. Since the JESD204 framer is now procedurally generated it is also very easy to support board or application specific requirements where the lane to converter ratio differs from the default (E.g. use 2 lanes/2 converters instead of 4 lanes/2 converters). This new core is primarily based on the existing axi_ad9144. For the time being the core is not user instantiatable and will only be used as a based to re-implement the converter specific cores. It will be extended in the future to allow user instantiation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| Makefile | ||
| ad_ip_jesd204_tpl_dac.v | ||
| ad_ip_jesd204_tpl_dac_channel.v | ||
| ad_ip_jesd204_tpl_dac_core.v | ||
| ad_ip_jesd204_tpl_dac_framer.v | ||
| ad_ip_jesd204_tpl_dac_hw.tcl | ||
| ad_ip_jesd204_tpl_dac_ip.tcl | ||
| ad_ip_jesd204_tpl_dac_regmap.v | ||