87 lines
2.9 KiB
Tcl
87 lines
2.9 KiB
Tcl
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package require qsys
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_alt.tcl
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set_module_property NAME axi_ad9152
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set_module_property DESCRIPTION "AXI AD9152 Interface"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME axi_ad9152
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# files
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ad_ip_files axi_ad9152 [list \
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$ad_hdl_dir/library/altera/common/ad_mul.v \
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$ad_hdl_dir/library/common/ad_dds_sine.v \
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$ad_hdl_dir/library/common/ad_dds_1.v \
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$ad_hdl_dir/library/common/ad_dds.v \
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$ad_hdl_dir/library/common/ad_rst.v \
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$ad_hdl_dir/library/common/up_axi.v \
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$ad_hdl_dir/library/common/up_xfer_cntrl.v \
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$ad_hdl_dir/library/common/up_xfer_status.v \
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$ad_hdl_dir/library/common/up_clock_mon.v \
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$ad_hdl_dir/library/common/up_dac_common.v \
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$ad_hdl_dir/library/common/up_dac_channel.v \
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\
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$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v \
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$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v \
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$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v \
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$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v \
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$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v \
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\
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axi_ad9152.v \
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$ad_hdl_dir/library/altera/common/up_xfer_cntrl_constr.sdc \
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$ad_hdl_dir/library/altera/common/up_xfer_status_constr.sdc \
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$ad_hdl_dir/library/altera/common/up_clock_mon_constr.sdc \
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$ad_hdl_dir/library/altera/common/up_rst_constr.sdc \
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]
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# parameters
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add_parameter ID INTEGER 0
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set_parameter_property ID DEFAULT_VALUE 0
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set_parameter_property ID DISPLAY_NAME ID
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set_parameter_property ID TYPE INTEGER
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set_parameter_property ID UNITS None
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set_parameter_property ID HDL_PARAMETER true
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# axi4 slave
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ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
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# transceiver interface
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ad_alt_intf clock tx_clk input 1
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add_interface if_tx_data avalon_streaming source
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add_interface_port if_tx_data tx_data data output 128
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add_interface_port if_tx_data tx_valid valid output 1
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add_interface_port if_tx_data tx_ready ready input 1
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set_interface_property if_tx_data associatedClock if_tx_clk
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set_interface_property if_tx_data dataBitsPerSymbol 128
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# dma interface
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ad_alt_intf clock dac_clk output 1
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add_interface dac_ch_0 conduit end
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add_interface_port dac_ch_0 dac_enable_0 enable Output 1
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add_interface_port dac_ch_0 dac_valid_0 valid Output 1
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add_interface_port dac_ch_0 dac_ddata_0 data Input 64
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set_interface_property dac_ch_0 associatedClock if_tx_clk
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set_interface_property dac_ch_0 associatedReset none
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add_interface dac_ch_1 conduit end
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add_interface_port dac_ch_1 dac_enable_1 enable Output 1
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add_interface_port dac_ch_1 dac_valid_1 valid Output 1
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add_interface_port dac_ch_1 dac_ddata_1 data Input 64
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set_interface_property dac_ch_1 associatedClock if_tx_clk
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set_interface_property dac_ch_1 associatedReset none
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ad_alt_intf signal dac_dunf input 1 unf
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