424 lines
16 KiB
Verilog
424 lines
16 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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//------------------------------------------------------------------------------
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//----------- Module Declaration -----------------------------------------------
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//------------------------------------------------------------------------------
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module ad7175_if
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(
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// Clock and Reset signals
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input fpga_clk_i,
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input adc_clk_i,
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input reset_n_i,
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// Conversion control signals
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input start_conversion_i,
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output [31:0] dma_data_o,
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output dma_data_rdy_o,
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// Transmit data on request signals
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input start_transmission_i,
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input [31:0] tx_data_i,
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output tx_data_rdy_o,
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// Read data on request signals
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input start_read_i,
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output [31:0] rx_data_o,
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output rx_data_rdy_o,
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// AD7175 IC control signals
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input adc_sdo_i,
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output adc_sdi_o,
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output adc_cs_o,
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output adc_sclk_o,
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// ADC status
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output reg adc_status_o
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);
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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// State Machine Registers
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reg [10:0] present_state; // Present FSM State
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reg [10:0] next_state; // Next FSM State
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reg [10:0] present_state_m1; // Used to synchronise FSM States between different clock domains
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// SCLK Registers
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reg [7:0] sclk_cnt; // Used to count SCLK Ticks
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reg [7:0] sclk_demand; // Used to set number of SCLK Ticks
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// Transmit Data Registers
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reg [47:0] tx_data_reg; // Used to shift data out
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reg [47:0] tx_data_reg_switch; // Used to select data that is being sent
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reg tx_data_rdy_int; // Used to signal the end of a transmit cycle
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// Receive Data Registers
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reg [47:0] rx_data_reg; // Used to shift data in
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reg [31:0] rx_read_data_reg; // Used to store read data
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reg rx_data_rdy_int; // Used to signal the end of a read cycle
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// Conversion Data Registers
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reg [31:0] dma_rx_data_reg; // Used to store conversion result (STATUS_REG[31:24] + DATA_REG[23:0])
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reg dma_rdy_int; // Used to signal the end of a conversion read
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// Internal registers used for external ports
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reg adc_sdi_o_int; // Used for adc_sdi_o
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reg cs_int; // Used for adc_cs_o
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//------------------------------------------------------------------------------
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//----------- Wires Declarations -----------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//----------- Local Parameters -------------------------------------------------
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//------------------------------------------------------------------------------
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// ADC Controller State Machine States
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parameter ADC_IDLE_STATE = 11'b00000000001; // Waits for Start Conversion / Start Transmission / Start Read
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parameter ADC_WAIT_FOR_DATA_STATE = 11'b00000000010; // Waits for adc_sdo_i to go low (signals new data is available)
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parameter ADC_PREP_READ_RESULT_STATE = 11'b00000000100; // Prepares data to perform Status + Data Register Read
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parameter ADC_READ_RESULT_STATE = 11'b00000001000; // Reads Status + Data Register
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parameter ADC_READ_RESULT_DONE_STATE = 11'b00000010000; // Signals completion of Status + Data Register Read
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parameter ADC_PREP_SEND_DATA_STATE = 11'b00000100000; // Prepares data to perform Data Transmit
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parameter ADC_SEND_DATA_STATE = 11'b00001000000; // Transmit Data
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parameter ADC_SEND_DATA_DONE_STATE = 11'b00010000000; // Signals completion of Data Transmission
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parameter ADC_PREP_READ_DATA_STATE = 11'b00100000000; // Prepares data to perform Data Read
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parameter ADC_READ_DATA_STATE = 11'b01000000000; // Reads Data
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parameter ADC_READ_DATA_DONE_STATE = 11'b10000000000; // Signals completion of Data Read
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// Number of SCLK Periods required for Status + Data Read
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parameter ADC_SCLK_PERIODS = 8'd48;
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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assign adc_sdi_o = adc_sdi_o_int;
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assign adc_sclk_o = (((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE))&&(sclk_cnt != 8'd0)) ? adc_clk_i : 1'b1;
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assign dma_data_o = dma_rx_data_reg;
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assign dma_data_rdy_o = dma_rdy_int;
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assign adc_cs_o = cs_int;
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assign tx_data_rdy_o = tx_data_rdy_int;
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assign rx_data_o = rx_read_data_reg;
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assign rx_data_rdy_o = rx_data_rdy_int;
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// Register States
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always @(posedge fpga_clk_i)
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begin
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if(reset_n_i == 1'b0)
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begin
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present_state <= ADC_IDLE_STATE;
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adc_status_o <= 1'b0;
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end
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else
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begin
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present_state <= next_state;
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adc_status_o <= 1'b1;
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end
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end
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// State switch logic
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always @(posedge fpga_clk_i)
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begin
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next_state <= present_state;
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case(present_state)
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ADC_IDLE_STATE:
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begin
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// If transmit data is required
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if(start_transmission_i == 1'b1)
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begin
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next_state <= ADC_PREP_SEND_DATA_STATE;
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end
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// If read data is required
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else if(start_read_i == 1'b1)
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begin
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next_state <= ADC_PREP_READ_DATA_STATE;
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end
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// If start conversion has been requested
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else if(start_conversion_i == 1'b1)
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begin
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next_state <= ADC_WAIT_FOR_DATA_STATE;
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end
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end
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ADC_WAIT_FOR_DATA_STATE:
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begin
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// If new data is available
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if(adc_sdo_i == 1'b0)
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begin
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next_state <= ADC_PREP_READ_RESULT_STATE;
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end
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// If transmit data is required
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else if(start_transmission_i == 1'b1)
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begin
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next_state <= ADC_PREP_SEND_DATA_STATE;
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end
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// If read data is required
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else if(start_read_i == 1'b1)
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begin
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next_state <= ADC_PREP_READ_DATA_STATE;
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end
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// If transmit data is not required anymore
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else if(start_conversion_i == 1'b0)
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begin
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next_state <= ADC_IDLE_STATE;
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end
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end
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ADC_PREP_READ_RESULT_STATE:
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begin
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if(present_state_m1 == ADC_PREP_READ_RESULT_STATE)
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begin
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next_state <= ADC_READ_RESULT_STATE;
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end
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end
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ADC_READ_RESULT_STATE:
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begin
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// If data has been sent
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if(sclk_cnt == 8'd0)
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begin
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next_state <= ADC_READ_RESULT_DONE_STATE;
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end
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end
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ADC_READ_RESULT_DONE_STATE:
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begin
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next_state <= ADC_IDLE_STATE;
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end
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ADC_PREP_SEND_DATA_STATE:
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begin
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if(present_state_m1 == ADC_PREP_SEND_DATA_STATE)
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begin
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next_state <= ADC_SEND_DATA_STATE;
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end
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end
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ADC_SEND_DATA_STATE:
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begin
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// If data has been sent
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if(sclk_cnt == 8'd0)
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begin
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next_state <= ADC_SEND_DATA_DONE_STATE;
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end
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end
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ADC_SEND_DATA_DONE_STATE:
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begin
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next_state <= ADC_IDLE_STATE;
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end
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ADC_PREP_READ_DATA_STATE:
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begin
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if(present_state_m1 == ADC_PREP_READ_DATA_STATE)
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begin
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next_state <= ADC_READ_DATA_STATE;
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end
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end
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ADC_READ_DATA_STATE:
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begin
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// If data has been sent
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if(sclk_cnt == 8'd0)
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begin
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next_state <= ADC_READ_DATA_DONE_STATE;
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end
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end
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ADC_READ_DATA_DONE_STATE:
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begin
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next_state <= ADC_IDLE_STATE;
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end
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default:
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begin
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next_state <= ADC_IDLE_STATE;
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end
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endcase
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end
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// State output logic
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always @(posedge fpga_clk_i)
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begin
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if(reset_n_i == 1'b0)
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begin
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dma_rdy_int <= 1'b0;
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cs_int <= 1'b1;
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tx_data_rdy_int <= 1'b0;
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rx_data_rdy_int <= 1'b0;
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end
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else
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begin
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case(present_state)
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ADC_IDLE_STATE:
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begin
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dma_rdy_int <= 1'b0;
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tx_data_rdy_int <= 1'b0;
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rx_data_rdy_int <= 1'b0;
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cs_int <= 1'b1;
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end
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ADC_WAIT_FOR_DATA_STATE:
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begin
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cs_int <= 1'b0;
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end
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ADC_PREP_READ_RESULT_STATE:
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begin
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dma_rdy_int <= 1'b0;
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tx_data_reg_switch <= 48'h400044000000;
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cs_int <= 1'b0;
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end
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ADC_READ_RESULT_STATE:
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begin
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dma_rdy_int <= 1'b0;
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cs_int <= 1'b0;
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end
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ADC_READ_RESULT_DONE_STATE:
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begin
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// Final data = Status Reg + Data Reg
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dma_rx_data_reg <= {rx_data_reg[39:32], rx_data_reg[23:0]};
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dma_rdy_int <= 1'b1;
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cs_int <= 1'b1;
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end
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ADC_PREP_SEND_DATA_STATE:
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begin
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// Maximum 32 bits transmission (that is why I add 16'd0 to the LSB)
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tx_data_rdy_int <= 1'b1;
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cs_int <= 1'b1;
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tx_data_reg_switch <= {tx_data_i, 16'd0};
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end
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ADC_SEND_DATA_STATE:
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begin
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tx_data_rdy_int <= 1'b0;
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cs_int <= 1'b0;
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end
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ADC_SEND_DATA_DONE_STATE:
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begin
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tx_data_rdy_int <= 1'b1;
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cs_int <= 1'b1;
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end
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ADC_PREP_READ_DATA_STATE:
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begin
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// Maximum 32 bits transmission (that is why I add 16'd0 to the LSB)
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cs_int <= 1'b1;
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rx_data_rdy_int <= 1'b1;
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tx_data_reg_switch <= {2'b01, tx_data_i[29:0], 16'd0};
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end
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ADC_READ_DATA_STATE:
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begin
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cs_int <= 1'b0;
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rx_data_rdy_int <= 1'b0;
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end
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ADC_READ_DATA_DONE_STATE:
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begin
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rx_read_data_reg <= rx_data_reg[31:0];
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cs_int <= 1'b1;
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rx_data_rdy_int <= 1'b1;
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end
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default:
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begin
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tx_data_rdy_int <= 1'b0;
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rx_data_rdy_int <= 1'b0;
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dma_rdy_int <= 1'b0;
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cs_int <= 1'b1;
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end
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endcase
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end
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end
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// Synchronise States between different clock domains
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always @(posedge adc_clk_i)
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begin
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present_state_m1 <= present_state;
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end
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// Select size of transfered data according to desired registers (see AD7176_2 Datasheet for details)
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always @(posedge fpga_clk_i)
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begin
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case(tx_data_i[29:24])
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6'h00:
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begin
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sclk_demand <= 8'd16;
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end
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6'h01, 6'h02, 6'h06, 6'h07, 6'h10, 6'h11, 6'h12, 6'h13, 6'h20, 6'h21, 6'h22, 6'h23, 6'h28, 6'h29, 6'h2a, 6'h2b:
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begin
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sclk_demand <= 8'd24;
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end
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6'h03, 6'h04, 6'h30, 6'h31, 6'h32, 6'h33, 6'h38, 6'h39, 6'h3a, 6'h3b:
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begin
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sclk_demand <= 8'd32;
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end
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default:
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begin
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sclk_demand <= 8'd16;
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end
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endcase
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end
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// Serial Data In
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always @(posedge adc_clk_i)
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begin
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if((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE))
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begin
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sclk_cnt <= sclk_cnt - 8'd1;
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rx_data_reg <= {rx_data_reg[46:0], adc_sdo_i};
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end
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else
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begin
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if((present_state_m1 == ADC_PREP_SEND_DATA_STATE)||(present_state_m1 == ADC_PREP_READ_DATA_STATE))
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begin
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sclk_cnt <= sclk_demand;
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end
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else
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begin
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sclk_cnt <= ADC_SCLK_PERIODS;
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end
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if(present_state_m1 == ADC_IDLE_STATE)
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begin
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rx_data_reg <= 48'd0;
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end
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end
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end
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// Serial Data Out
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always @(negedge adc_clk_i)
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begin
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if((present_state_m1 == ADC_READ_RESULT_STATE)||(present_state_m1 == ADC_SEND_DATA_STATE)||(present_state_m1 == ADC_READ_DATA_STATE))
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begin
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adc_sdi_o_int <= tx_data_reg[47];
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tx_data_reg <= {tx_data_reg[46:0], 1'b0};
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end
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else
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begin
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tx_data_reg <= tx_data_reg_switch;
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end
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end
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endmodule
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