319 lines
9.1 KiB
Verilog
319 lines
9.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
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// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ps/1ps
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module ad_serdes_in #(
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parameter DEVICE_TYPE = 0,
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parameter DDR_OR_SDR_N = 0,
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parameter SERDES_FACTOR = 8,
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parameter DATA_WIDTH = 16,
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parameter IODELAY_CTRL = 0,
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parameter IODELAY_GROUP = "dev_if_delay_group") (
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// reset and clocks
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input rst,
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input clk,
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input div_clk,
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input loaden,
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input [ 7:0] phase,
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input locked,
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// data interface
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output [(DATA_WIDTH-1):0] data_s0,
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output [(DATA_WIDTH-1):0] data_s1,
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output [(DATA_WIDTH-1):0] data_s2,
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output [(DATA_WIDTH-1):0] data_s3,
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output [(DATA_WIDTH-1):0] data_s4,
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output [(DATA_WIDTH-1):0] data_s5,
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output [(DATA_WIDTH-1):0] data_s6,
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output [(DATA_WIDTH-1):0] data_s7,
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input [(DATA_WIDTH-1):0] data_in_p,
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input [(DATA_WIDTH-1):0] data_in_n,
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// delay-data interface
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input up_clk,
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input [(DATA_WIDTH-1):0] up_dld,
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input [((DATA_WIDTH*5)-1):0] up_dwdata,
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output [((DATA_WIDTH*5)-1):0] up_drdata,
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// delay-control interface
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input delay_clk,
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input delay_rst,
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output delay_locked);
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localparam DEVICE_6SERIES = 1;
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localparam DEVICE_7SERIES = 0;
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localparam DATA_RATE = (DDR_OR_SDR_N) ? "DDR" : "SDR";
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// internal signals
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wire [(DATA_WIDTH-1):0] data_in_ibuf_s;
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wire [(DATA_WIDTH-1):0] data_in_idelay_s;
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wire [(DATA_WIDTH-1):0] data_shift1_s;
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wire [(DATA_WIDTH-1):0] data_shift2_s;
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// delay controller
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generate
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if (IODELAY_CTRL == 1) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYCTRL i_delay_ctrl (
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.RST (delay_rst),
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.REFCLK (delay_clk),
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.RDY (delay_locked));
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end else begin
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assign delay_locked = 1'b1;
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end
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endgenerate
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// received data interface: ibuf -> idelay -> iserdes
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genvar l_inst;
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generate
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for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
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IBUFDS i_ibuf (
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.I (data_in_p[l_inst]),
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.IB (data_in_n[l_inst]),
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.O (data_in_ibuf_s[l_inst]));
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if (DEVICE_TYPE == DEVICE_7SERIES) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYE2 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("IDATAIN"),
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.HIGH_PERFORMANCE_MODE ("FALSE"),
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.IDELAY_TYPE ("VAR_LOAD"),
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.IDELAY_VALUE (0),
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.REFCLK_FREQUENCY (200.0),
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.PIPE_SEL ("FALSE"),
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.SIGNAL_PATTERN ("DATA"))
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i_idelay (
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.CE (1'b0),
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.INC (1'b0),
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.DATAIN (1'b0),
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.LDPIPEEN (1'b0),
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.CINVCTRL (1'b0),
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.REGRST (1'b0),
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.C (up_clk),
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.IDATAIN (data_in_ibuf_s[l_inst]),
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.DATAOUT (data_in_idelay_s[l_inst]),
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.LD (up_dld[l_inst]),
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.CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]),
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.CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)]));
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end
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if(DEVICE_TYPE == DEVICE_6SERIES) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IODELAYE1 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("I"),
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.HIGH_PERFORMANCE_MODE ("TRUE"),
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.IDELAY_TYPE ("VAR_LOADABLE"),
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.IDELAY_VALUE (0),
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.ODELAY_TYPE ("FIXED"),
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.ODELAY_VALUE (0),
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.REFCLK_FREQUENCY (200.0),
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.SIGNAL_PATTERN ("DATA"))
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i_idelay (
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.T (1'b1),
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.CE (1'b0),
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.INC (1'b0),
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.CLKIN (1'b0),
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.DATAIN (1'b0),
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.ODATAIN (1'b0),
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.CINVCTRL (1'b0),
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.C (up_clk),
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.IDATAIN (data_in_ibuf_s[l_inst]),
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.DATAOUT (data_in_idelay_s[l_inst]),
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.RST (up_dld[l_inst]),
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.CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]),
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.CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)]));
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end
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if (DEVICE_TYPE == DEVICE_7SERIES) begin
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ISERDESE2 #(
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.DATA_RATE (DATA_RATE),
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.DATA_WIDTH (SERDES_FACTOR),
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.DYN_CLKDIV_INV_EN ("FALSE"),
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.DYN_CLK_INV_EN ("FALSE"),
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.INIT_Q1 (1'b0),
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.INIT_Q2 (1'b0),
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.INIT_Q3 (1'b0),
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.INIT_Q4 (1'b0),
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.INTERFACE_TYPE ("NETWORKING"),
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.IOBDELAY ("IFD"),
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.NUM_CE (2),
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.OFB_USED ("FALSE"),
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.SERDES_MODE ("MASTER"),
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.SRVAL_Q1 (1'b0),
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.SRVAL_Q2 (1'b0),
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.SRVAL_Q3 (1'b0),
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.SRVAL_Q4 (1'b0))
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i_iserdes (
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.O (),
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.Q1 (data_s0[l_inst]),
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.Q2 (data_s1[l_inst]),
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.Q3 (data_s2[l_inst]),
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.Q4 (data_s3[l_inst]),
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.Q5 (data_s4[l_inst]),
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.Q6 (data_s5[l_inst]),
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.Q7 (data_s6[l_inst]),
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.Q8 (data_s7[l_inst]),
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.SHIFTOUT1 (),
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.SHIFTOUT2 (),
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.BITSLIP (1'b0),
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.CE1 (1'b1),
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.CE2 (1'b1),
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.CLKDIVP (1'b0),
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.CLK (clk),
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.CLKB (~clk),
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.CLKDIV (div_clk),
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.OCLK (1'b0),
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.DYNCLKDIVSEL (1'b0),
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.DYNCLKSEL (1'b0),
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.D (1'b0),
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.DDLY (data_in_idelay_s[l_inst]),
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.OFB (1'b0),
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.OCLKB (1'b0),
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.RST (rst),
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.SHIFTIN1 (1'b0),
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.SHIFTIN2 (1'b0));
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end
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if (DEVICE_TYPE == DEVICE_6SERIES) begin
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ISERDESE1 #(
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.DATA_RATE (DATA_RATE),
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.DATA_WIDTH (SERDES_FACTOR),
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.DYN_CLKDIV_INV_EN ("FALSE"),
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.DYN_CLK_INV_EN ("FALSE"),
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.INIT_Q1 (1'b0),
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.INIT_Q2 (1'b0),
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.INIT_Q3 (1'b0),
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.INIT_Q4 (1'b0),
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.INTERFACE_TYPE ("NETWORKING"),
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.IOBDELAY ("NONE"),
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.NUM_CE (1),
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.OFB_USED ("FALSE"),
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.SERDES_MODE ("MASTER"),
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.SRVAL_Q1 (1'b0),
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.SRVAL_Q2 (1'b0),
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.SRVAL_Q3 (1'b0),
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.SRVAL_Q4 (1'b0))
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i_iserdes_m (
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.O (),
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.Q1 (data_s0[l_inst]),
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.Q2 (data_s1[l_inst]),
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.Q3 (data_s2[l_inst]),
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.Q4 (data_s3[l_inst]),
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.Q5 (data_s4[l_inst]),
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.Q6 (data_s5[l_inst]),
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.SHIFTOUT1 (data_shift1_s[l_inst]),
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.SHIFTOUT2 (data_shift2_s[l_inst]),
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.BITSLIP (1'b0),
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.CE1 (1'b1),
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.CE2 (1'b1),
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.CLK (clk),
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.CLKB (~clk),
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.CLKDIV (div_clk),
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.OCLK (1'b0),
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.DYNCLKDIVSEL (1'b0),
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.DYNCLKSEL (1'b0),
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.D (1'b0),
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.DDLY (data_in_idelay_s[l_inst]),
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.OFB (1'b0),
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.RST (rst),
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.SHIFTIN1 (1'b0),
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.SHIFTIN2 (1'b0));
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ISERDESE1 #(
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.DATA_RATE (DATA_RATE),
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.DATA_WIDTH (SERDES_FACTOR),
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.DYN_CLKDIV_INV_EN ("FALSE"),
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.DYN_CLK_INV_EN ("FALSE"),
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.INIT_Q1 (1'b0),
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.INIT_Q2 (1'b0),
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.INIT_Q3 (1'b0),
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.INIT_Q4 (1'b0),
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.INTERFACE_TYPE ("NETWORKING"),
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.IOBDELAY ("NONE"),
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.NUM_CE (1),
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.OFB_USED ("FALSE"),
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.SERDES_MODE ("SLAVE"),
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.SRVAL_Q1 (1'b0),
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.SRVAL_Q2 (1'b0),
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.SRVAL_Q3 (1'b0),
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.SRVAL_Q4 (1'b0))
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i_iserdes_s (
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.O (),
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.Q1 (),
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.Q2 (),
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.Q3 (data_s6[l_inst]),
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.Q4 (data_s7[l_inst]),
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.Q5 (),
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.Q6 (),
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.SHIFTOUT1 (),
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.SHIFTOUT2 (),
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.BITSLIP (1'b0),
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.CE1 (1'b1),
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.CE2 (1'b1),
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.CLK (clk),
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.CLKB (~clk),
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.CLKDIV (div_clk),
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.OCLK (1'b0),
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.DYNCLKDIVSEL (1'b0),
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.DYNCLKSEL (1'b0),
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.D (1'b0),
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.DDLY (data_in_idelay_s[l_inst]),
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.OFB (1'b0),
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.RST (rst),
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.SHIFTIN1 (data_shift1_s[l_inst]),
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.SHIFTIN2 (data_shift2_s[l_inst]));
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end
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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