47 lines
1.5 KiB
Tcl
47 lines
1.5 KiB
Tcl
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package require qsys
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_alt.tcl
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ad_ip_create util_upack {Channel Unpack Utility} util_upack_elab
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ad_ip_files util_upack [list\
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util_upack_dmx.v \
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util_upack_dsf.v \
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util_upack.v]
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# parameters
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ad_ip_parameter CHANNEL_DATA_WIDTH INTEGER 32
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ad_ip_parameter NUM_OF_CHANNELS INTEGER 8
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# defaults
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ad_alt_intf clock dac_clk input 1
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ad_alt_intf signal dac_valid output 1 valid
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ad_alt_intf signal dac_sync output 1 sync
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ad_alt_intf signal dac_data input NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH data
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add_interface dac_ch_0 conduit end
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add_interface_port dac_ch_0 dac_enable_0 enable Input 1
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add_interface_port dac_ch_0 dac_valid_0 valid Input 1
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add_interface_port dac_ch_0 dac_valid_out_0 data_valid Output 1
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add_interface_port dac_ch_0 dac_data_0 data Output CHANNEL_DATA_WIDTH
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set_interface_property dac_ch_0 associatedClock if_dac_clk
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set_interface_property dac_ch_0 associatedReset none
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proc util_upack_elab {} {
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for {set n 1} {$n < 8} {incr n} {
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if {[get_parameter_value NUM_OF_CHANNELS] > $n} {
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add_interface dac_ch_${n} conduit end
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add_interface_port dac_ch_${n} dac_enable_${n} enable Input 1
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add_interface_port dac_ch_${n} dac_valid_${n} valid Input 1
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add_interface_port dac_ch_${n} dac_valid_out_${n} data_valid Output 1
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add_interface_port dac_ch_${n} dac_data_${n} data Output CHANNEL_DATA_WIDTH
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set_interface_property dac_ch_${n} associatedClock if_dac_clk
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set_interface_property dac_ch_${n} associatedReset none
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}
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}
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}
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