Istvan Csomortani 7c9bc40c75 axi_ad9361&TDD: Update TDD ... + Delete unnecessary registers + Add the module ad_addsub.v to resolve additions and subtractions inside TDD control + Redefine the burst logic + Redesign the control signal generations + Note: This patch fix the TDD related timing violations		2015-05-13 14:03:01 +03:00
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Makefile	axi_ad9361_tdd: Initial commit.	2015-05-11 12:20:44 +03:00
axi_ad9361.v	axi_ad9361_tdd: Initial commit.	2015-05-11 12:20:44 +03:00
axi_ad9361_alt_lvds_rx.v	Remove executable flags from non-exectuable files	2014-09-09 15:05:06 +02:00
axi_ad9361_alt_lvds_tx.v	Remove executable flags from non-exectuable files	2014-09-09 15:05:06 +02:00
axi_ad9361_constr.xdc	axi_ad9361: Add ASYNC_REG properties to CDC regs and add missing -datapath_only	2015-04-21 10:15:02 +02:00
axi_ad9361_dev_if.v	ad9361- align hold	2015-05-11 11:55:01 -04:00
axi_ad9361_dev_if_alt.v	axi_ad9361: changed device interface module for Altera to have the same inputs as the one for Xilinx	2015-05-08 17:43:10 +03:00
axi_ad9361_hw.tcl	axi_ad9361: Remove the Altera toplevel wrapper	2014-09-11 12:29:13 +02:00
axi_ad9361_ip.tcl	axi_ad9361&TDD: Update TDD	2015-05-13 14:03:01 +03:00
axi_ad9361_rx.v	ad9361- framing modifications	2015-05-07 15:13:18 -04:00
axi_ad9361_rx_channel.v	up/constr: independent read/write and local constraints	2014-10-02 14:35:59 -04:00
axi_ad9361_rx_pnmon.v	Remove executable flags from non-exectuable files	2014-09-09 15:05:06 +02:00
axi_ad9361_tdd.v	axi_ad9361&TDD: Update TDD	2015-05-13 14:03:01 +03:00
axi_ad9361_tdd_if.v	axi_ad9361_tdd: Initial commit.	2015-05-11 12:20:44 +03:00
axi_ad9361_tx.v	up/constr: independent read/write and local constraints	2014-10-02 14:35:59 -04:00
axi_ad9361_tx_channel.v	up/constr: independent read/write and local constraints	2014-10-02 14:35:59 -04:00