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Lars-Peter Clausen c9206433b5 adi_ip.tcl: Allow to specify processing order for adi_ip_constraints 
In order to be able to use get_clocks in a constraint file the constraint
file needs to run after the constraint file that creates the clock. Allow to
specify the processing order when adding a constraint file to a core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2015-04-15 17:20:15 +02:00
library adi_ip.tcl: Allow to specify processing order for adi_ip_constraints 2015-04-15 17:20:15 +02:00
projects Makefile: Updated makefiles. Added makefiles for altera 2015-04-09 17:57:06 +03:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md README: Update Vivado version number, 2014.4.1 is the new supported version 2015-03-03 09:48:13 +02:00

README.md

hdl

Analog Devices HDL libraries and projects

Tools version:

  • Vivado 2014.4.1
  • Quartus 14.0

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga