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pluto_hdl_adi/library/axi_dmac
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Lars-Peter Clausen c8900eb8ab axi_dmac: burst_memory: Move src valid bytes resizing to resize_src module 
The handling of the src_data_valid_bytes signal and its related signal is
tightly coupled to the behavior of the resize_src module. The code that
handles it makes assumptions about the internal behavior of the resize_src
module.

Move the handling of the src_data_valid_bytes signal when upsizing the data
bus into the resize_src module so that all the code that is related is in
the same place and the code outside of the module does not have to care
about the internals.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2018-11-30 23:41:49 +02:00
..
bd axi_dmac: fix address width detection 2018-07-20 18:12:24 +03:00
tb axi_dmac: burst_memory: Consider DMA_LENGTH_ALIGN 2018-11-30 23:41:49 +02:00
2d_transfer.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
Makefile axi_dmac: early abort support 2018-09-07 11:38:04 +03:00
address_generator.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac.v axi_dmac: burst_memory: Consider DMA_LENGTH_ALIGN 2018-11-30 23:41:49 +02:00
axi_dmac_burst_memory.v axi_dmac: burst_memory: Move src valid bytes resizing to resize_src module 2018-11-30 23:41:49 +02:00
axi_dmac_constr.sdc axi_dmac: preparation work for reporting length of partial transfers 2018-09-07 11:38:04 +03:00
axi_dmac_constr.ttcl axi_dmac: early abort support 2018-09-07 11:38:04 +03:00
axi_dmac_hw.tcl axi_dmac: early abort support 2018-09-07 11:38:04 +03:00
axi_dmac_ip.tcl axi_dmac: preparation work for reporting length of partial transfers 2018-09-07 11:38:04 +03:00
axi_dmac_pkg_sv.ttcl axi_dmac: ttcl file support for simulation 2018-07-11 11:30:22 +03:00
axi_dmac_regmap.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac_regmap_request.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac_reset_manager.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac_resize_dest.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac_resize_src.v axi_dmac: burst_memory: Move src valid bytes resizing to resize_src module 2018-11-30 23:41:49 +02:00
axi_dmac_response_manager.v axi_dmac: burst_memory: Reset beat counter at the end of each burst 2018-11-30 23:41:49 +02:00
axi_dmac_transfer.v axi_dmac: burst_memory: Consider DMA_LENGTH_ALIGN 2018-11-30 23:41:49 +02:00
axi_register_slice.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
data_mover.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
dest_axi_mm.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
dest_axi_stream.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
dest_fifo_inf.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
inc_id.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
request_arb.v axi_dmac: burst_memory: Consider DMA_LENGTH_ALIGN 2018-11-30 23:41:49 +02:00
request_generator.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
resp.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
response_generator.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
response_handler.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
splitter.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
src_axi_mm.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
src_axi_stream.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
src_fifo_inf.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00