Adrian Costina 74b922f9f8 axi_*: Infer clock and reset signals of an IP ... A clock sink must be connected to clock source, and a reset sink to reset source, otherwise the tool will throw a synthesis warning. By properly inferring all the reset and clock signals of an IP, we can get rid of unwanted warning messages. The following IPs tcl script was updated: - axi_ad9434 - axi_hdmi_tx - util_cpack - util_adxcvr - axi_ad6676 - axi_ad9625 - axi_ad9379 - axi_ad9265 - util_tdd_sync - util_rfifo - util_wfifo - axi_ad9361 - axi_ad9467 - util_upack - axi_dacfifo - axi_ad9152 - axi_ad9680 - util_clkdiv - axi_ad9122 - axi_ad9684 - axi_mc_speed - axi_mc_current_monitor - axi_mc_controller - util_gmii_to_rgmii - util_adxcvr - axi_ad9379 - axi_hdmi - library - axi_fmcadc5_sync - util_adcfifo - util_mfifo - axi_jesd204_rx - axi_jesd204_tx - axi_ad9361 - axi_adxcvr_ip		2018-04-11 15:09:54 +03:00
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Makefile	hdlmake.pl- updates	2017-08-07 16:09:20 -04:00
axi_dac_interpolate.v	axi_dac_interpolate: Add correction at the begining of the interpolation chain	2017-08-03 17:21:37 +03:00
axi_dac_interpolate_constr.xdc	axi_dac_interpolate: Make dac_reset external	2017-04-18 12:17:39 +02:00
axi_dac_interpolate_filter.v	axi_dac_interpolate: Add correction at the begining of the interpolation chain	2017-08-03 17:21:37 +03:00
axi_dac_interpolate_ip.tcl	axi_*: Infer clock and reset signals of an IP	2018-04-11 15:09:54 +03:00
axi_dac_interpolate_reg.v	axi_dac_interpolate: Add correction at the begining of the interpolation chain	2017-08-03 17:21:37 +03:00
cic_interp.v	axi_dac_interpolate: Initial commit	2017-01-31 16:22:49 +02:00
fir_interp.v	axi_dac_interpolate: Initial commit	2017-01-31 16:22:49 +02:00
m2k_interp.m	axi_dac_interpolate: Added matlab file for interpolation filters	2017-07-21 14:37:27 +03:00