315 lines
9.9 KiB
Verilog
315 lines
9.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dac_interpolate #(
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parameter CORRECTION_DISABLE = 1) (
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input dac_clk,
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input dac_rst,
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input [15:0] dac_data_a,
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input [15:0] dac_data_b,
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input dac_valid_a,
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input dac_valid_b,
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input dma_valid_a,
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input dma_valid_b,
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output dma_ready_a,
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output dma_ready_b,
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input dac_enable_a,
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input dac_enable_b,
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output [15:0] dac_int_data_a,
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output [15:0] dac_int_data_b,
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output underflow,
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input [ 1:0] trigger_i,
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input trigger_adc,
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input trigger_la,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [ 6:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [ 6:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready);
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reg [ 1:0] trigger_i_m1;
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reg [ 1:0] trigger_i_m2;
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reg [ 1:0] trigger_i_m3;
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reg trigger_adc_m1;
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reg trigger_adc_m2;
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reg trigger_adc_m3;
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reg trigger_la_m1;
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reg trigger_la_m2;
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reg trigger_la_m3;
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reg [ 1:0] any_edge_trigger;
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reg [ 1:0] rise_edge_trigger;
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reg [ 1:0] fall_edge_trigger;
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reg [ 1:0] high_level_trigger;
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reg [ 1:0] low_level_trigger;
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// internal signals
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wire up_clk;
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wire up_rstn;
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wire [ 4:0] up_waddr;
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wire [31:0] up_wdata;
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wire up_wack;
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wire up_wreq;
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wire up_rack;
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wire [31:0] up_rdata;
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wire up_rreq;
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wire [ 4:0] up_raddr;
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wire [31:0] interpolation_ratio_a;
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wire [31:0] interpolation_ratio_b;
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wire [ 2:0] filter_mask_a;
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wire [ 2:0] filter_mask_b;
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wire dma_transfer_suspend;
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wire start_sync_channels;
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wire dac_correction_enable_a;
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wire dac_correction_enable_b;
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wire [15:0] dac_correction_coefficient_a;
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wire [15:0] dac_correction_coefficient_b;
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wire [19:0] trigger_config;
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wire [ 1:0] en_trigger_pins;
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wire en_trigger_adc;
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wire en_trigger_la;
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wire [ 1:0] low_level;
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wire [ 1:0] high_level;
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wire [ 1:0] any_edge;
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wire [ 1:0] rise_edge;
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wire [ 1:0] fall_edge;
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wire trigger_active;
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wire ext_trigger;
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wire underflow_a;
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wire underflow_b;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// trigger logic
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assign low_level = trigger_config[1:0];
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assign high_level = trigger_config[3:2];
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assign any_edge = trigger_config[5:4];
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assign rise_edge = trigger_config[7:6];
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assign fall_edge = trigger_config[9:8];
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assign en_trigger_pins = trigger_config[17:16];
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assign en_trigger_adc = trigger_config[18];
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assign en_trigger_la = trigger_config[19];
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assign trigger_active = |trigger_config[19:16];
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assign trigger = (ext_trigger & en_trigger_pins) |
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(trigger_adc_m2 & en_trigger_adc) |
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(trigger_la_m2 & en_trigger_la);
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assign ext_trigger = |(any_edge_trigger |
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rise_edge_trigger |
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fall_edge_trigger |
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high_level_trigger |
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low_level_trigger);
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// sync
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always @(posedge dac_clk) begin
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trigger_i_m1 <= trigger_i;
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trigger_i_m2 <= trigger_i_m1;
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trigger_i_m3 <= trigger_i_m2;
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trigger_adc_m1 <= trigger_adc;
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trigger_adc_m2 <= trigger_adc_m1;
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trigger_la_m1 <= trigger_la;
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trigger_la_m2 <= trigger_la_m1;
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end
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always @(posedge dac_clk) begin
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any_edge_trigger <= (trigger_i_m3 ^ trigger_i_m2) & any_edge;
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rise_edge_trigger <= (~trigger_i_m3 & trigger_i_m2) & rise_edge;
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fall_edge_trigger <= (trigger_i_m3 & ~trigger_i_m2) & fall_edge;
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high_level_trigger <= trigger_i_m3 & high_level;
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low_level_trigger <= ~trigger_i_m3 & low_level;
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end
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assign underflow = underflow_a | underflow_b;
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axi_dac_interpolate_filter #(
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.CORRECTION_DISABLE(CORRECTION_DISABLE))
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i_filter_a (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_data (dac_data_a),
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.dac_valid (dac_valid_a),
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.dac_enable (dac_enable_a),
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.dac_int_data (dac_int_data_a),
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.dma_ready (dma_ready_a),
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.underflow (underflow_a),
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.filter_mask (filter_mask_a),
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.interpolation_ratio (interpolation_ratio_a),
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.dma_transfer_suspend (dma_transfer_suspend),
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.start_sync_channels (start_sync_channels),
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.trigger (trigger),
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.trigger_active (trigger_active),
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.dma_valid (dma_valid_a),
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.dma_valid_adjacent (dma_valid_b),
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.dac_correction_enable(dac_correction_enable_a),
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.dac_correction_coefficient(dac_correction_coefficient_a)
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);
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axi_dac_interpolate_filter #(
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.CORRECTION_DISABLE(CORRECTION_DISABLE))
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i_filter_b (
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.dac_clk (dac_clk),
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.dac_rst (dac_rst),
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.dac_data (dac_data_b),
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.dac_valid (dac_valid_b),
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.underflow (underflow_b),
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.dac_enable (dac_enable_b),
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.dac_int_data (dac_int_data_b),
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.dma_ready (dma_ready_b),
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.filter_mask (filter_mask_b),
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.interpolation_ratio (interpolation_ratio_b),
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.dma_transfer_suspend (dma_transfer_suspend),
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.start_sync_channels (start_sync_channels),
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.trigger (trigger),
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.trigger_active (trigger_active),
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.dma_valid (dma_valid_b),
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.dma_valid_adjacent (dma_valid_a),
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.dac_correction_enable(dac_correction_enable_b),
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.dac_correction_coefficient(dac_correction_coefficient_b)
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);
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axi_dac_interpolate_reg axi_dac_interpolate_reg_inst (
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.clk (dac_clk),
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.dac_interpolation_ratio_a (interpolation_ratio_a),
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.dac_filter_mask_a (filter_mask_a),
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.dac_interpolation_ratio_b (interpolation_ratio_b),
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.dac_filter_mask_b (filter_mask_b),
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.dma_transfer_suspend (dma_transfer_suspend),
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.start_sync_channels (start_sync_channels),
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.dac_correction_enable_a(dac_correction_enable_a),
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.dac_correction_enable_b(dac_correction_enable_b),
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.dac_correction_coefficient_a(dac_correction_coefficient_a),
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.dac_correction_coefficient_b(dac_correction_coefficient_b),
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.trigger_config (trigger_config),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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up_axi #(
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.AXI_ADDRESS_WIDTH(7)
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) i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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