AndreiGrozav 0e002f2f31 daq3_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V		2017-03-09 08:50:55 +02:00
..
Makefile	updated makefiles	2016-12-09 23:06:41 +02:00
system_constr.sdc	daq3/a10gx/system_constr.sdc- fix typo	2017-02-03 09:26:07 -05:00
system_project.tcl	daq3_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V	2017-03-09 08:50:55 +02:00
system_qsys.tcl	projects/altera* - default & common qsys commands	2016-12-20 16:27:44 -05:00
system_top.v	a10gx- xilinx/altera sync-up	2017-01-30 10:01:28 -05:00