Laszlo Nagy c5c772127d up_delay_cntrl:ad_serdes_in: Make delay value width parametrizable ... US/US+ devices have IDELAY/ODELAY with 512 taps. This requires wider control value for delay selection. 9 bits contrary to 5 on 7series.		2020-08-07 08:31:19 +03:00
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ad_data_clk.v	Add FPGA info parameters flow	2019-03-30 11:26:11 +02:00
ad_data_in.v	iodelay: Expose the REFCLK_FREQUENCY parameter	2019-06-11 18:13:06 +03:00
ad_data_out.v	iodelay: Expose the REFCLK_FREQUENCY parameter	2019-06-11 18:13:06 +03:00
ad_dcfilter.v	Move Xilinx specific DC filter implementation to library/xilinx/common/	2018-04-11 15:09:54 +03:00
ad_iobuf.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
ad_mmcm_drp.v	Add FPGA info parameters flow	2019-03-30 11:26:11 +02:00
ad_mul.v	ad_mul.v: Add parameters for A and B input widths	2018-07-18 18:19:30 +03:00
ad_rst_constr.xdc	ad_rst_constr: Added the quiet option	2020-01-20 15:26:48 +02:00
ad_serdes_clk.v	Add FPGA info parameters flow	2019-03-30 11:26:11 +02:00
ad_serdes_in.v	up_delay_cntrl:ad_serdes_in: Make delay value width parametrizable	2020-08-07 08:31:19 +03:00
ad_serdes_out.v	common/ad_serdes_out.v: Add US/US+ support	2020-08-07 08:31:19 +03:00
up_clock_mon_constr.xdc	up_clk_mon_constr: -heir is deprecated, use hierarchical instead	2020-01-13 12:25:23 +02:00
up_xfer_cntrl_constr.xdc	restructure: Move xilinx specific constraints to /library/xilinx/common/	2017-03-30 16:16:02 +03:00
up_xfer_status_constr.xdc	restructure: Move xilinx specific constraints to /library/xilinx/common/	2017-03-30 16:16:02 +03:00