Istvan Csomortani ac2e5a9dac constraints: Update constraints ... Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.		2017-02-24 13:43:32 +02:00
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Makefile	Makefiles: fixed axi_adxcvr/util_adxcvr Makefiles to include interfaces dependancy	2017-02-23 16:16:34 +02:00
util_adxcvr.v	util_adxcvr: expose cpll/qpll as it is	2016-11-22 11:32:37 -05:00
util_adxcvr_constr.xdc	constraints: Update constraints	2017-02-24 13:43:32 +02:00
util_adxcvr_ip.tcl	xcvr updates- board procedure	2016-11-22 14:43:36 -05:00
util_adxcvr_xch.v	util_adxcvr: expose cpll/qpll as it is	2016-11-22 11:32:37 -05:00
util_adxcvr_xcm.v	Fix warnings	2016-11-14 15:17:15 +02:00