Istvan Csomortani ac2e5a9dac constraints: Update constraints ... Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.		2017-02-24 13:43:32 +02:00
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Makefile	updated makefiles	2016-12-09 23:06:41 +02:00
axi_xcvrlb.v	axi_xcvrlb- updates	2016-09-19 12:39:59 -04:00
axi_xcvrlb_1.v	library/axi_xcvrlb- xcvr changes	2016-11-23 12:00:13 -05:00
axi_xcvrlb_constr.xdc	constraints: Update constraints	2017-02-24 13:43:32 +02:00
axi_xcvrlb_ip.tcl	axi_xcvrlb- constraints	2016-09-21 11:04:22 -04:00