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For some reason, if a core has an AXI and an AXI Stream interface too, the tool sets the AXI interface's ASSOCIATED_RESET parameter to the AXI Stream interface's reset. This cause an unconnected AXI reset port in the block design. This 'set_property' command intended to overwrite this automated setup. |
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README.md
#HDL Reference Designs
Analog Devices HDL libraries and projects
###Tools version:
- Xilinx : Vivado 2014.4.1
- Altera : Quartus 15.0
###Documentation and support
For first time users, it is highly recommended to go through our HDL user guide.
For support please visit our FPGA Reference Designs Support Community on EngineerZone.