Istvan Csomortani 07956cfe66 spi_engine: Define parameter inside the module statement ... Part of the effort to update all verilog files to use the ANSI-C style port list in module definitions. (verilog-2001)		2017-05-04 12:13:47 +03:00
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Makefile	updated makefiles	2016-12-09 23:06:41 +02:00
axi_spi_engine.v	spi_engine: Define parameter inside the module statement	2017-05-04 12:13:47 +03:00
axi_spi_engine_ip.tcl	axi_spi_engine: Define ports dependencies for up_* interface	2017-04-27 11:27:35 +03:00