stefan.raus 9413afa41c jesd204_rx_constr.ttcl: Remove ASYNC_REG constraint from i_lmfc/cdc_sync_stage1_reg ... get_cell on i_lmfc/cdc_sync_stage1_reg doesn't return anything because design was updated. This generates a CRITICAL WARNING and since the constraint it not necessary anymore, it can be deleted.		2021-03-22 10:55:00 +02:00
..
bd	jesd204: Xilinx: NP=12 support	2021-02-05 15:24:15 +02:00
Makefile	jesd204: Xilinx: NP=12 support	2021-02-05 15:24:15 +02:00
align_mux.v	jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement	2021-02-05 15:24:15 +02:00
elastic_buffer.v	jesd204: Xilinx: NP=12 support	2021-02-05 15:24:15 +02:00
error_monitor.v	jesd204_rx: 64b mode support for receive peripheral	2020-02-10 09:47:07 +02:00
jesd204_ilas_monitor.v	jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement	2021-02-05 15:24:15 +02:00
jesd204_lane_latency_monitor.v	jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement	2021-02-05 15:24:15 +02:00
jesd204_rx.v	jesd204/jesd204_rx: Make output pipeline stages opt in feature	2021-03-08 10:46:52 +02:00
jesd204_rx_cgs.v	Add missing timescale annotations	2018-10-17 10:32:47 +03:00
jesd204_rx_constr.sdc	jesd204: Intel: NP12 support	2021-02-05 15:24:15 +02:00
jesd204_rx_constr.ttcl	jesd204_rx_constr.ttcl: Remove ASYNC_REG constraint from i_lmfc/cdc_sync_stage1_reg	2021-03-22 10:55:00 +02:00
jesd204_rx_ctrl.v	jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement	2021-02-05 15:24:15 +02:00
jesd204_rx_ctrl_64b.v	jesd204_rx:jesd204_rx_ctrl_64b: Improve timing closure	2021-03-08 10:46:52 +02:00
jesd204_rx_frame_align.v	jesd204: Xilinx: NP=12 support	2021-02-05 15:24:15 +02:00
jesd204_rx_header.v	jesd204_rx: 64b mode support for receive peripheral	2020-02-10 09:47:07 +02:00
jesd204_rx_hw.tcl	Update Quartus Prime version from 19.3.0 to 20.1.0	2021-03-08 11:29:33 +02:00
jesd204_rx_ip.tcl	jesd204: Expose core synthesis parameters through registers	2021-02-05 15:24:15 +02:00
jesd204_rx_lane.v	jesd204: Xilinx: NP=12 support	2021-02-05 15:24:15 +02:00
jesd204_rx_lane_64b.v	jesd204_rx:64b: Remove reset	2021-03-08 10:46:52 +02:00