Adrian Costina 0f37dd6424 fmcjesdadc1: Fixed project ... - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release		2016-02-19 14:09:57 +02:00
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fmcjesdadc1_bd.qsys	fmcjesdadc1: Fixed project	2016-02-19 14:09:57 +02:00
fmcjesdadc1_bd.tcl	fmcjesdadc1: Updated project to 2015.2.1	2015-09-24 19:12:40 +03:00
fmcjesdadc1_spi.v	a5soc: fixes for 14.0 and spi conflicts	2014-08-11 16:46:37 -04:00