Adrian Costina 0f37dd6424 fmcjesdadc1: Fixed project ... - changed system_project.tcl so that all base designs to be included - changed DMA properties to take into consideration the new parameter names - changed reset bridges to asynchronous - increased maximum burst size of the DMA bridge - changed the data_width of the memory bus to 256, as with 512 timing violations may occur - changed base addresses for the base system to be the same as in the previous release		2016-02-19 14:09:57 +02:00
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a5gt	fmcjesdadc1: Fixed project	2016-02-19 14:09:57 +02:00
a5soc	Makefiles: Removed " from path	2015-11-27 14:02:46 +02:00
common	fmcjesdadc1: Fixed project	2016-02-19 14:09:57 +02:00
kc705	fmcjesdadc1: Updated KC705 project for maximum throughput from DMA to DDR	2016-02-09 12:00:27 +02:00
vc707	fmcjesdadc1: Updated VC707 project for maximum throughput from DMA to DDR	2016-02-09 12:30:56 +02:00
zc706	fmcjesdadc1: Added clock constraint for the ADC path	2016-01-22 15:46:20 +02:00
Makefile	Makefiles: Update makefiles to include the nerw axi_gpreg / util_mfifo libraries	2015-11-10 09:32:50 +02:00