pluto_hdl_adi/library/xilinx/axi_dacfifo
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
..
Makefile hdlmake updates 2017-04-25 15:46:26 -04:00
axi_dacfifo.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_dacfifo_constr.sdc adc/dac-fifo altera cores 2017-02-28 13:30:50 -05:00
axi_dacfifo_constr.xdc constraints: Update constraints 2017-02-24 13:43:32 +02:00
axi_dacfifo_dac.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_dacfifo_hw.tcl altera- default to latest version 2017-05-12 13:25:17 -04:00
axi_dacfifo_ip.tcl axi_dacfifo: Move the axi_dac_fifo_bypass module to util_dac_fifo_bypass 2017-04-21 13:23:03 +03:00
axi_dacfifo_rd.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00
axi_dacfifo_wr.v all: Update license for all hdl source files 2017-05-17 11:52:08 +03:00