Lars-Peter Clausen 558f2e89af imageon: zc706: Fix ddr and fixed_io signal names ... The toplevel input/output signal names are lower case, but the signals connected to the system_wrapper are upper case. Since verilog is case sensitive this leaves the toplevel input/output signals unconnected. Fix this by using lower case names everywhere. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2015-04-23 14:33:47 +02:00
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Makefile	Makefile: Added top level Makefile. Modified behavior of clean and clean-all	2015-04-17 17:22:38 +03:00
system_bd.tcl	imageon: Initial commit	2015-01-08 17:01:22 +02:00
system_constr.xdc	imageon_zc706: Update project	2015-04-01 18:50:18 +03:00
system_project.tcl	imageon: updates	2015-03-24 15:08:48 -04:00
system_top.v	imageon: zc706: Fix ddr and fixed_io signal names	2015-04-23 14:33:47 +02:00