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Lars-Peter Clausen bd6c76f4ab fmcomms5: Set DMA AXI type to AXI3 on ZYNQ The HP memory ports on ZYNQ are AXI3. The AXI-DMAC supports both native AXI3 and AXI4, by configuring it for AXI3 there is no need for a protocol converter inside the interconnect, that connects the DMAC to the HP port. In addition to that also set the data width for the DMAC on the HP port side to 64 so there is no need for a memory width converter in the interconnect. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2015-04-23 14:33:47 +02:00
library	library: Modified the adi_ip.tcl script	2015-04-23 14:31:23 +03:00
projects	fmcomms5: Set DMA AXI type to AXI3 on ZYNQ	2015-04-23 14:33:47 +02:00
.gitignore	a5soc: increase pipeline for qsys	2014-05-04 10:38:53 -04:00
LICENSE	Update LICENSE	2014-03-11 15:06:52 -04:00
Makefile	Makefile: Added top level Makefile. Modified behavior of clean and clean-all	2015-04-17 17:22:38 +03:00
README.md	README: Update Vivado version number, 2014.4.1 is the new supported version	2015-03-03 09:48:13 +02:00

README.md

hdl

Analog Devices HDL libraries and projects

Tools version:

Vivado 2014.4.1
Quartus 14.0

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga