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Istvan Csomortani bb185296d7 fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples. 
The 2^18 dma address width with a 64 dma data width will result a FIFO, what will be implemented by 512 RAMB36 cells.
This is a the maximum BRAM FIFO depth in case of the VC707.
 		2015-04-23 18:00:00 +03:00
library util_gmii_to_rgmii: Added constraints 2015-04-23 16:53:57 +03:00
projects fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples. 2015-04-23 18:00:00 +03:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README: Update Vivado version number, 2014.4.1 is the new supported version 2015-03-03 09:48:13 +02:00

README.md

hdl

Analog Devices HDL libraries and projects

Tools version:

  • Vivado 2014.4.1
  • Quartus 14.0

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga