caosjr bad1d03678 spi_engine: Fixup param ranges and CPHA info (#1239) ... Set validation ranges for DATA_WIDTH and NUM_OF_CS for the expected min/max values in the verilog source code. Also, fix swapped description for CPHA in the documentation. Signed-off-by: Carlos Oliveira <caosjr8@gmail.com>		2023-12-18 10:52:26 -03:00
..
extensions	docs: Add component diagram generator	2023-12-13 10:38:29 -03:00
library	spi_engine: Fixup param ranges and CPHA info (#1239)	2023-12-18 10:52:26 -03:00
projects	docs: General improvements	2023-12-13 10:38:29 -03:00
regmap	docs: Include the DMA SG documentation	2023-12-04 14:34:33 +02:00
sources	docs: Add component diagram generator	2023-12-13 10:38:29 -03:00
user_guide	docs: Add component diagram generator	2023-12-13 10:38:29 -03:00
Makefile	docs: General improvements	2023-12-13 10:38:29 -03:00
conf.py	docs: Add component diagram generator	2023-12-13 10:38:29 -03:00
index.rst	docs: Add ad5766 documentation (#1227)	2023-12-12 12:12:47 +02:00
make.bat	docs: Include sphinx documentation	2023-09-27 14:36:34 -03:00
requirements.txt	docs: Add component diagram generator	2023-12-13 10:38:29 -03:00