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pluto_hdl_adi/library/axi_adrv9001
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alin724 f8c82c611d axi_adrv9001: Add support for symbol operation mode on Xilinx devices 
Add CMOS support for the interface for the following symbol modes on Xilinx devices:

A              B  C       D                     E       F      G            H
CSSI__1-lane   1  16/8    80(SDR)/160(DDR)      80      -      SDR/DDR      SDR/DDR->4/2(C=16), 2/1(C=8)

Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate

CSSI - CMOS Source Synchronous Interface
 		2021-08-17 15:33:06 +03:00
..
intel axi_adrv9001: Populate correct ratio of the SSI interface and user interface clocks 2021-05-26 15:44:45 +03:00
Makefile makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
adrv9001_aligner4.v axi_adrv9001:rx: Add reset to link layer 2021-05-26 15:44:45 +03:00
adrv9001_aligner8.v axi_adrv9001:rx: Add reset to link layer 2021-05-26 15:44:45 +03:00
adrv9001_pack.v axi_adrv9001:rx: Add reset to link layer 2021-05-26 15:44:45 +03:00
adrv9001_rx.v adrv9001: fixes for reset metastability on xilinx ioserdes 2021-07-09 11:11:04 +03:00
adrv9001_rx_link.v axi_adrv9001: Add support for symbol operation mode on Xilinx devices 2021-08-17 15:33:06 +03:00
adrv9001_tx.v adrv9001: fixes for reset metastability on xilinx ioserdes 2021-07-09 11:11:04 +03:00
adrv9001_tx_link.v axi_adrv9001: Add support for symbol operation mode on Xilinx devices 2021-08-17 15:33:06 +03:00
axi_adrv9001.v axi_adrv9001: Add support for symbol operation mode on Xilinx devices 2021-08-17 15:33:06 +03:00
axi_adrv9001_constr.sdc axi_adrv9001: Double sync control lines between interface 1 and 2 2021-03-04 11:13:10 +02:00
axi_adrv9001_constr.xdc axi_adrv9001: Double sync control lines between interface 1 and 2 2021-03-04 11:13:10 +02:00
axi_adrv9001_core.v axi_adrv9001: Add support for symbol operation mode on Xilinx devices 2021-08-17 15:33:06 +03:00
axi_adrv9001_hw.tcl Update Quartus version to 20.4 2021-08-12 11:15:01 +03:00
axi_adrv9001_if.v axi_adrv9001: Add support for symbol operation mode on Xilinx devices 2021-08-17 15:33:06 +03:00
axi_adrv9001_ip.tcl axi_adrv9001: Add TDD support 2021-01-20 13:00:01 +02:00
axi_adrv9001_rx.v axi_adrv9001: Add support for symbol operation mode on Xilinx devices 2021-08-17 15:33:06 +03:00
axi_adrv9001_rx_channel.v axi_adrv9001: Add support for symbol operation mode on Xilinx devices 2021-08-17 15:33:06 +03:00
axi_adrv9001_tdd.v axi_adrv9001: Let gate signals have initial value, useful for simulation 2021-05-26 15:44:45 +03:00
axi_adrv9001_tx.v axi_adrv9001: Add support for symbol operation mode on Xilinx devices 2021-08-17 15:33:06 +03:00
axi_adrv9001_tx_channel.v library:axi_adrv9001: Initial version 2020-08-24 17:49:12 +03:00