242 lines
7.4 KiB
Verilog
242 lines
7.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory of
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// the repository (LICENSE_GPL2), and at: <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// clock and resets
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input sys_clk,
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input sys_resetn,
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// ddr3
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output ddr3_clk_p,
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output ddr3_clk_n,
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output [ 13:0] ddr3_a,
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output [ 2:0] ddr3_ba,
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output ddr3_cke,
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output ddr3_cs_n,
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output ddr3_odt,
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output ddr3_reset_n,
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output ddr3_we_n,
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output ddr3_ras_n,
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output ddr3_cas_n,
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inout [ 7:0] ddr3_dqs_p,
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inout [ 7:0] ddr3_dqs_n,
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inout [ 63:0] ddr3_dq,
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output [ 7:0] ddr3_dm,
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input ddr3_rzq,
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// ethernet
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input eth_rx_clk,
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input [ 3:0] eth_rx_data,
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input eth_rx_cntrl,
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output eth_tx_clk_out,
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output [ 3:0] eth_tx_data,
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output eth_tx_cntrl,
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output eth_mdc,
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input eth_mdio_i,
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output eth_mdio_o,
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output eth_mdio_t,
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output eth_phy_resetn,
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// board gpio
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output [ 15:0] gpio_bd_o,
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input [ 10:0] gpio_bd_i,
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// lane interface
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input ref_clk,
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input [ 3:0] rx_data,
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output rx_sync,
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output rx_sysref,
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// spi
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output spi_csn,
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output spi_clk,
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inout spi_sdio);
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// internal registers
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reg [ 3:0] phy_rst_cnt = 0;
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reg phy_rst_reg = 0;
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// internal signals
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wire sys_125m_clk;
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wire sys_25m_clk;
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wire sys_2m5_clk;
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wire sys_cpu_clk;
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wire sys_cpu_mem_resetn;
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wire sys_cpu_resetn;
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wire sys_pll_locked;
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wire eth_tx_clk;
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wire eth_tx_mode_1g;
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wire eth_tx_mode_10m_100m_n;
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wire rx_clk;
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wire [ 3:0] rx_ip_sof;
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wire [127:0] rx_ip_data;
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wire spi_mosi;
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wire spi_miso;
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wire [ 63:0] gpio_i;
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wire [ 63:0] gpio_o;
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wire [ 7:0] spi_csn_s;
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// sys reset
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assign sys_cpu_resetn = sys_resetn & sys_cpu_mem_resetn & sys_pll_locked;
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// ethernet transmit clock
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assign eth_tx_clk = (eth_tx_mode_1g == 1'b1) ? sys_125m_clk :
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(eth_tx_mode_10m_100m_n == 1'b0) ? sys_25m_clk : sys_2m5_clk;
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assign eth_phy_resetn = phy_rst_reg;
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always@ (posedge eth_mdc) begin
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phy_rst_cnt <= phy_rst_cnt + 4'd1;
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if (phy_rst_cnt == 4'h0) begin
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phy_rst_reg <= sys_pll_locked;
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end
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end
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// gpio
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assign gpio_i[63:11] = gpio_o[63:11];
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assign gpio_i[10: 0] = gpio_bd_i;
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assign gpio_bd_o = gpio_o[26:11];
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// sysref
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ad_sysref_gen #(.SYSREF_PERIOD(64)) i_sysref (
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.core_clk (rx_clk),
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.sysref_en (gpio_o[32]),
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.sysref_out (rx_sysref));
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// instantiations
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assign spi_csn = spi_csn_s[0];
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fmcjesdadc1_spi i_fmcjesdadc1_spi (
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.spi_csn (spi_csn_s[0]),
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.spi_clk (spi_clk),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso),
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.spi_sdio (spi_sdio));
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altddio_out #(.width(1)) i_eth_tx_clk_out (
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.aset (1'b0),
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.sset (1'b0),
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.sclr (1'b0),
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.oe (1'b1),
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.oe_out (),
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.datain_h (1'b1),
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.datain_l (1'b0),
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.outclocken (1'b1),
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.aclr (~sys_pll_locked),
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.outclock (eth_tx_clk),
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.dataout (eth_tx_clk_out));
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system_bd i_system_bd (
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.rx_core_clk_clk (rx_clk),
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.rx_data_0_rx_serial_data (rx_data[0]),
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.rx_data_1_rx_serial_data (rx_data[1]),
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.rx_data_2_rx_serial_data (rx_data[2]),
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.rx_data_3_rx_serial_data (rx_data[3]),
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.rx_ip_data_data (rx_ip_data),
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.rx_ip_data_valid (),
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.rx_ip_data_ready (1'b1),
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.rx_ip_data_0_data (rx_ip_data[63:0]),
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.rx_ip_data_0_valid (1'b1),
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.rx_ip_data_0_ready (),
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.rx_ip_data_1_data (rx_ip_data[127:64]),
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.rx_ip_data_1_valid (1'b1),
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.rx_ip_data_1_ready (),
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.rx_ip_sof_export (rx_ip_sof),
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.rx_ip_sof_0_export (rx_ip_sof),
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.rx_ip_sof_1_export (rx_ip_sof),
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.rx_ref_clk_clk (ref_clk),
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.rx_sync_export (rx_sync),
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.rx_sysref_export (rx_sysref),
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.sys_125m_clk_clk (sys_125m_clk),
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.sys_25m_clk_clk (sys_25m_clk),
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.sys_2m5_clk_clk (sys_2m5_clk),
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.sys_clk_clk (sys_cpu_clk),
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.sys_cpu_clk_clk (sys_cpu_clk),
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.sys_cpu_reset_reset_n (sys_cpu_mem_resetn),
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.sys_ddr3_cntrl_mem_mem_a (ddr3_a),
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.sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
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.sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
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.sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
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.sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
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.sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
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.sys_ddr3_cntrl_mem_mem_dm (ddr3_dm),
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.sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
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.sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
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.sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
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.sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
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.sys_ddr3_cntrl_mem_mem_dq (ddr3_dq),
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.sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p),
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.sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n),
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.sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
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.sys_ddr3_cntrl_oct_rzqin (ddr3_rzq),
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.sys_ethernet_mdio_mdc (eth_mdc),
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.sys_ethernet_mdio_mdio_in (eth_mdio_i),
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.sys_ethernet_mdio_mdio_out (eth_mdio_o),
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.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
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.sys_ethernet_rgmii_rgmii_in (eth_rx_data),
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.sys_ethernet_rgmii_rgmii_out (eth_tx_data),
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.sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
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.sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
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.sys_ethernet_rx_clk_clk (eth_rx_clk),
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.sys_ethernet_status_set_10 (),
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.sys_ethernet_status_set_1000 (),
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.sys_ethernet_status_eth_mode (eth_tx_mode_1g),
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.sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n),
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.sys_ethernet_tx_clk_clk (eth_tx_clk),
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.sys_gpio_bd_in_port (gpio_i[31:0]),
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.sys_gpio_bd_out_port (gpio_o[31:0]),
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.sys_gpio_in_export (gpio_i[63:32]),
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.sys_gpio_out_export (gpio_o[63:32]),
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.sys_pll_locked_export (sys_pll_locked),
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.sys_ref_clk_clk (sys_clk),
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.sys_ref_rst_reset_n (sys_resetn),
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.sys_rst_reset_n (sys_cpu_resetn),
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.sys_spi_MISO (spi_miso),
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.sys_spi_MOSI (spi_mosi),
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.sys_spi_SCLK (spi_clk),
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.sys_spi_SS_n (spi_csn_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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