56 lines
2.0 KiB
Verilog
56 lines
2.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory of
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// the repository (LICENSE_GPL2), and at: <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ns
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module prcfg_adc #(
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parameter CHANNEL_ID = 0) (
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input clk,
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// control ports
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input [31:0] control,
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output [31:0] status,
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// FIFO interface
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input src_adc_enable,
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input src_adc_valid,
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input [15:0] src_adc_data,
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output reg dst_adc_enable,
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output reg dst_adc_valid,
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output reg [15:0] dst_adc_data);
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localparam RP_ID = 8'hA0;
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assign status = {24'h0, RP_ID};
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always @(posedge clk) begin
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dst_adc_enable <= src_adc_enable;
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dst_adc_valid <= src_adc_valid;
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dst_adc_data <= src_adc_data;
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end
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endmodule
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