hotoleanudan cc68bd5198 fmcjesdadc1: Update block design (#743) ... Modified the project such that there is only one data path for the ADC data: deleted one of the JESD tpl instances, one of the cpack instances and one of the dma instances. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>		2021-09-08 17:19:57 +03:00
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Makefile	fmcjesdadc1: Update block design (#743)	2021-09-08 17:19:57 +03:00
system_bd.tcl	sysid: Upgrade framework, header/ip are now at 2/1.1.a	2021-01-20 01:02:56 +02:00
system_constr.xdc	fmcjesdadc1: Change rx_div_clk to 125MHz	2019-11-20 10:50:18 +02:00
system_project.tcl	library: Move ad_iobuf to the common library, as it's not Xilinx specific	2020-11-02 16:13:35 +02:00
system_top.v	all/system_top.v: loopback gpio lines	2018-10-04 14:19:37 +03:00