44 lines
1.6 KiB
Tcl
44 lines
1.6 KiB
Tcl
# ip
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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adi_ip_create axi_tdd
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adi_ip_files axi_tdd [list \
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"$ad_hdl_dir/library/common/ad_addsub.v" \
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"$ad_hdl_dir/library/common/ad_tdd_control.v" \
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"$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
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"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
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"$ad_hdl_dir/library/common/up_xfer_status.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
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"axi_tdd_constr.xdc" \
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"axi_tdd.v" ]
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adi_ip_properties axi_tdd
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set_property display_name "ADI AXI TDD Controller" [ipx::current_core]
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set_property description "ADI AXI TDD Controller" [ipx::current_core]
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adi_init_bd_tcl
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proc add_reset {name polarity} {
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set reset_intf [ipx::infer_bus_interface $name xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
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set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf]
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set_property value $polarity $reset_polarity
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}
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ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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add_reset rst ACTIVE_HIGH
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add_reset s_axi_aresetn ACTIVE_LOW
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ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]
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set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF -of_objects [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]]
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ipx::create_xgui_files [ipx::current_core]
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ipx::save_core [ipx::current_core]
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