114 lines
3.5 KiB
Verilog
114 lines
3.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_slave #(
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parameter DATA_WIDTH = 32,
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parameter ACCEPTANCE = 3,
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parameter MIN_LATENCY = 16,
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parameter MAX_LATENCY = 32
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) (
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input clk,
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input reset,
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input valid,
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output ready,
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input [31:0] addr,
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input [7:0] len,
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input [2:0] size,
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input [1:0] burst,
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input [2:0] prot,
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input [3:0] cache,
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output beat_stb,
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input beat_ack,
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output [31:0] beat_addr,
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output beat_last
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);
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reg [31:0] timestamp = 'h00;
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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timestamp <= 'h00;
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end else begin
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timestamp <= timestamp + 1'b1;
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end
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end
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reg [32+32+8-1:0] req_fifo[0:15];
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reg [3:0] req_fifo_rd = 'h00;
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reg [3:0] req_fifo_wr = 'h00;
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wire [3:0] req_fifo_level = req_fifo_wr - req_fifo_rd;
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assign ready = req_fifo_level < ACCEPTANCE;
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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req_fifo_wr <= 'h00;
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end else begin
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if (valid == 1'b1 && ready == 1'b1) begin
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req_fifo[req_fifo_wr][71:40] <= timestamp + {$random} % (MAX_LATENCY - MIN_LATENCY + 1) + MIN_LATENCY;
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req_fifo[req_fifo_wr][39:0] <= {addr,len};
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req_fifo_wr <= req_fifo_wr + 1'b1;
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end
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end
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end
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reg [7:0] beat_counter = 'h00;
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assign beat_stb = req_fifo_level != 0 && timestamp > req_fifo[req_fifo_rd][71:40];
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assign beat_last = beat_stb ? beat_counter == req_fifo[req_fifo_rd][0+:8] : 1'b0;
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assign beat_addr = req_fifo[req_fifo_rd][8+:32] + beat_counter * DATA_WIDTH / 8;
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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beat_counter <= 'h00;
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req_fifo_rd <= 'h00;
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end else begin
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if (beat_ack == 1'b1) begin
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if (beat_last == 1'b1) begin
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beat_counter <= 'h00;
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req_fifo_rd <= req_fifo_rd + 1'b1;
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end else begin
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beat_counter <= beat_counter + 1'b1;
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end
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end
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end
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end
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endmodule
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