86 lines
2.3 KiB
Tcl
86 lines
2.3 KiB
Tcl
# ip
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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adi_ip_create axi_dacfifo
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adi_ip_files axi_dacfifo [list \
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"$ad_hdl_dir/library/common/ad_g2b.v" \
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"$ad_hdl_dir/library/common/ad_b2g.v" \
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"$ad_hdl_dir/library/common/ad_mem_asym.v" \
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"$ad_hdl_dir/library/common/ad_mem.v" \
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"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
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"$ad_hdl_dir/library/util_dacfifo/util_dacfifo_bypass.v" \
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"axi_dacfifo_constr.xdc" \
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"axi_dacfifo_wr.v" \
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"axi_dacfifo_rd.v" \
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"axi_dacfifo_address_buffer.v" \
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"axi_dacfifo.v"]
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adi_ip_properties_lite axi_dacfifo
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ipx::infer_bus_interface {\
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axi_awvalid \
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axi_awid \
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axi_awburst \
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axi_awlock \
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axi_awcache \
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axi_awprot \
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axi_awqos \
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axi_awlen \
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axi_awsize \
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axi_awaddr \
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axi_awready \
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axi_wvalid \
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axi_wdata \
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axi_wstrb \
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axi_wlast \
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axi_wready \
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axi_bvalid \
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axi_bid \
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axi_bresp \
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axi_bready \
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axi_arvalid \
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axi_arid \
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axi_arburst \
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axi_arlock \
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axi_arcache \
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axi_arprot \
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axi_arqos \
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axi_arlen \
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axi_arsize \
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axi_araddr \
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axi_arready \
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axi_rvalid \
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axi_rid \
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axi_rresp \
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axi_rlast \
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axi_rdata \
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axi_rready} \
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xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \
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-of_objects [ipx::current_core]]
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set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
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-of_objects [ipx::get_bus_interfaces axi_clk \
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-of_objects [ipx::current_core]]]
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ipx::add_address_space axi [ipx::current_core]
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set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \
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-of_objects [ipx::current_core]]
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set_property range 4294967296 [ipx::get_address_spaces axi \
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-of_objects [ipx::current_core]]
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set_property width 512 [ipx::get_address_spaces axi \
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-of_objects [ipx::current_core]]
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ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface dma_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
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ipx::save_core [ipx::current_core]
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