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The sync_data module can be used to continuously transfer multi-bit signals like status signals safely from the source to the destination clock domain. A transfer takes 2 source and 2 destination clock cycles. It is not guaranteed that all transitions on the source side will be visible on the target side if the signal is changing faster than this. Logic using this block should be aware of it. The primary intention is for it to be used for slowly changing status signals. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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