Adrian Costina ab8627e669 fmcomms1: Changed ILA data capture and sys constraints ... The ILA can not work at 250MHz on ZED/ZC702. Because of this, the data path was modified from 28bits@250MHz to 56bits@125MHz, by using a FIFO. The ZED/ZC702 max BUFG frequency is 464MHz, which corresponds to a 2.16 period so the constraints were modified accordingly.		2014-03-17 15:50:01 +02:00
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adv7511	Initial check in of VC707 base project	2014-03-10 17:26:17 +02:00
common	Merge branch 'master' of github.com:analogdevicesinc/hdl	2014-03-11 09:58:34 -04:00
fmcomms1	fmcomms1: Changed ILA data capture and sys constraints	2014-03-17 15:50:01 +02:00
fmcomms2	FMCOMMS2: Modified FCLK2 to 125 MHz, and xdc file	2014-03-14 16:27:56 +02:00
scripts	Fix default repository path for adi_project.tcl	2014-03-13 10:28:16 +02:00