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Adrian Costina ab8627e669 fmcomms1: Changed ILA data capture and sys constraints 
The ILA can not work at 250MHz on ZED/ZC702. Because of this, the data
path was modified from 28bits@250MHz to 56bits@125MHz, by using a FIFO.
The ZED/ZC702 max BUFG frequency is 464MHz, which corresponds to a 2.16
period so the constraints were modified accordingly.
 		2014-03-17 15:50:01 +02:00
library axi_dmac: Fix default value for DMA type 2014-03-17 13:20:49 +01:00
projects fmcomms1: Changed ILA data capture and sys constraints 2014-03-17 15:50:01 +02:00
.gitignore added gitignore 2014-03-05 10:47:16 -05:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Update README.md 2014-03-13 14:03:15 -04:00

README.md

hdl

Analog Devices HDL libraries and projects

http://wiki.analog.com/resources/fpga/docs/hdl/github

http://wiki.analog.com/resources/fpga/docs/hdl/regmap