155 lines
4.4 KiB
Verilog
155 lines
4.4 KiB
Verilog
// ***************************************************************************
|
|
// ***************************************************************************
|
|
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
|
//
|
|
// Each core or library found in this collection may have its own licensing terms.
|
|
// The user should keep this in in mind while exploring these cores.
|
|
//
|
|
// Redistribution and use in source and binary forms,
|
|
// with or without modification of this file, are permitted under the terms of either
|
|
// (at the option of the user):
|
|
//
|
|
// 1. The GNU General Public License version 2 as published by the
|
|
// Free Software Foundation, which can be found in the top level directory, or at:
|
|
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
|
|
//
|
|
// OR
|
|
//
|
|
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
|
|
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
|
|
//
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|
|
|
|
`timescale 1ns/100ps
|
|
|
|
module system_top (
|
|
inout [14:0] ddr_addr,
|
|
inout [ 2:0] ddr_ba,
|
|
inout ddr_cas_n,
|
|
inout ddr_ck_n,
|
|
inout ddr_ck_p,
|
|
inout ddr_cke,
|
|
inout ddr_cs_n,
|
|
inout [ 3:0] ddr_dm,
|
|
inout [31:0] ddr_dq,
|
|
inout [ 3:0] ddr_dqs_n,
|
|
inout [ 3:0] ddr_dqs_p,
|
|
inout ddr_odt,
|
|
inout ddr_ras_n,
|
|
inout ddr_reset_n,
|
|
inout ddr_we_n,
|
|
|
|
inout fixed_io_ddr_vrn,
|
|
inout fixed_io_ddr_vrp,
|
|
inout [53:0] fixed_io_mio,
|
|
inout fixed_io_ps_clk,
|
|
inout fixed_io_ps_porb,
|
|
inout fixed_io_ps_srstb,
|
|
|
|
inout spi_sdo,
|
|
input spi_sdi,
|
|
output [ 1:0] spi_cs,
|
|
output spi_sclk,
|
|
output led_clk_o,
|
|
output gain0_o,
|
|
output gain1_o,
|
|
|
|
input otg_vbusoc);
|
|
|
|
// internal signals
|
|
|
|
wire [34:0] gpio_i;
|
|
wire [34:0] gpio_o;
|
|
wire [34:0] gpio_t;
|
|
wire [23:0] offload_sdi_data;
|
|
|
|
wire spi_sdo_o;
|
|
wire spi_sdo_t;
|
|
wire excitation;
|
|
|
|
assign gain0_o = gpio_o[32];
|
|
assign gain1_o = gpio_o[33];
|
|
|
|
assign gpio_i[34] = spi_sdi; // Interrupt
|
|
assign gpio_i[33:0] = gpio_o[33:0];
|
|
assign led_clk_o = excitation;
|
|
|
|
ad_iobuf #(
|
|
.DATA_WIDTH(1)
|
|
) i_sdo_iobuf (
|
|
.dio_t(spi_sdo_t),
|
|
.dio_i(spi_sdo_o),
|
|
.dio_o(),
|
|
.dio_p(spi_sdo)
|
|
);
|
|
|
|
system_wrapper i_system_wrapper (
|
|
.ddr_addr (ddr_addr),
|
|
.ddr_ba (ddr_ba),
|
|
.ddr_cas_n (ddr_cas_n),
|
|
.ddr_ck_n (ddr_ck_n),
|
|
.ddr_ck_p (ddr_ck_p),
|
|
.ddr_cke (ddr_cke),
|
|
.ddr_cs_n (ddr_cs_n),
|
|
.ddr_dm (ddr_dm),
|
|
.ddr_dq (ddr_dq),
|
|
.ddr_dqs_n (ddr_dqs_n),
|
|
.ddr_dqs_p (ddr_dqs_p),
|
|
.ddr_odt (ddr_odt),
|
|
.ddr_ras_n (ddr_ras_n),
|
|
.ddr_reset_n (ddr_reset_n),
|
|
.ddr_we_n (ddr_we_n),
|
|
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
|
|
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
|
|
.fixed_io_mio (fixed_io_mio),
|
|
.fixed_io_ps_clk (fixed_io_ps_clk),
|
|
.fixed_io_ps_porb (fixed_io_ps_porb),
|
|
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
|
.gpio_i (gpio_i),
|
|
.gpio_o (gpio_o),
|
|
.gpio_t (gpio_t),
|
|
.ps_intr_00 (1'b0),
|
|
.ps_intr_01 (1'b0),
|
|
.ps_intr_02 (1'b0),
|
|
.ps_intr_03 (1'b0),
|
|
.ps_intr_04 (1'b0),
|
|
.ps_intr_05 (1'b0),
|
|
.ps_intr_06 (1'b0),
|
|
.ps_intr_07 (1'b0),
|
|
.ps_intr_08 (1'b0),
|
|
.ps_intr_09 (1'b0),
|
|
.ps_intr_11 (1'b0),
|
|
.ps_intr_14 (1'b0),
|
|
.ps_intr_15 (1'b0),
|
|
.ps_intr_10 (1'b0),
|
|
.spi0_clk_i (1'b0),
|
|
.spi0_clk_o (),
|
|
.spi0_csn_0_o (),
|
|
.spi0_csn_1_o (),
|
|
.spi0_csn_2_o (),
|
|
.spi0_csn_i (1'b1),
|
|
.spi0_sdi_i (),
|
|
.spi0_sdo_i (1'b0),
|
|
.spi0_sdo_o (),
|
|
.spi1_clk_i (1'b0),
|
|
.spi1_clk_o (),
|
|
.spi1_csn_0_o (),
|
|
.spi1_csn_1_o (),
|
|
.spi1_csn_2_o (),
|
|
.spi1_csn_i (1'b1),
|
|
.spi1_sdi_i (1'b0),
|
|
.spi1_sdo_i (1'b0),
|
|
.spi1_sdo_o (),
|
|
.spi_sdo (spi_sdo_o),
|
|
.spi_sdo_t (spi_sdo_t),
|
|
.spi_sdi (spi_sdi),
|
|
.spi_cs (spi_cs),
|
|
.spi_sclk (spi_sclk),
|
|
.excitation (excitation));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|