Adrian Costina 74b922f9f8 axi_*: Infer clock and reset signals of an IP ... A clock sink must be connected to clock source, and a reset sink to reset source, otherwise the tool will throw a synthesis warning. By properly inferring all the reset and clock signals of an IP, we can get rid of unwanted warning messages. The following IPs tcl script was updated: - axi_ad9434 - axi_hdmi_tx - util_cpack - util_adxcvr - axi_ad6676 - axi_ad9625 - axi_ad9379 - axi_ad9265 - util_tdd_sync - util_rfifo - util_wfifo - axi_ad9361 - axi_ad9467 - util_upack - axi_dacfifo - axi_ad9152 - axi_ad9680 - util_clkdiv - axi_ad9122 - axi_ad9684 - axi_mc_speed - axi_mc_current_monitor - axi_mc_controller - util_gmii_to_rgmii - util_adxcvr - axi_ad9379 - axi_hdmi - library - axi_fmcadc5_sync - util_adcfifo - util_mfifo - axi_jesd204_rx - axi_jesd204_tx - axi_ad9361 - axi_adxcvr_ip		2018-04-11 15:09:54 +03:00
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Makefile	updated makefiles	2016-12-09 23:06:41 +02:00
util_rfifo.v	rfifo- drive valid outs	2017-08-10 11:23:40 -04:00
util_rfifo_constr.sdc	rfifo/upack- changes	2017-07-28 16:18:54 -04:00
util_rfifo_constr.xdc	rfifo/upack- changes	2017-07-28 16:18:54 -04:00
util_rfifo_hw.tcl	rfifo/upack- changes	2017-07-28 16:18:54 -04:00
util_rfifo_ip.tcl	axi_*: Infer clock and reset signals of an IP	2018-04-11 15:09:54 +03:00