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Istvan Csomortani aa7b0bb4dd VC707 basesys: General fixes, actual status: working 
- Add an auxiliary cpu interconnect
	- Add an auxiliary interrupt concatenation module
	- Add new MIG file, current frequency of the DDR interface is 100
	  Mhz
	- Memory interconnect optimisation strategy is 'Maximize
	  Performance'
 		2014-03-24 13:07:48 +02:00
..
adv7511 VC707 basesys: General fixes, actual status: working 2014-03-24 13:07:48 +02:00
common VC707 basesys: General fixes, actual status: working 2014-03-24 13:07:48 +02:00
fmcomms1 fmcomms1: Changed ILA data capture and sys constraints 2014-03-17 15:50:01 +02:00
fmcomms2 FMCOMMS2 KC705 Project. 2014-03-24 11:48:52 +02:00
scripts Added phys_opt_design step for fixing timing 2014-03-19 16:42:44 +02:00