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Matthew Fornero aa3a821456 up_axi: Same cycle BVALID/READY fails on Altera 
The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.

Similar to:
2817ccdb22
("up_axi: altera can not handle same clock assertion of arready and rvalid")

Signed-off-by: Matthew Fornero <matt.fornero@mathworks.com>
 		2016-07-19 09:50:43 -07:00
library up_axi: Same cycle BVALID/READY fails on Altera 2016-07-19 09:50:43 -07:00
projects adi_project.pl: Fix ADI_NO_BITSTREAM_COMPRESSION detection logic 2016-07-14 11:33:56 +02:00
.gitattributes Add .gitattributes file 2015-06-26 11:07:10 +02:00
.gitignore ignore gui 2015-09-22 16:32:02 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update the README 2016-05-26 09:09:42 +03:00

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