a98bc88b84
The current framer implementation is limited in that it only supports N'=16 and either S=1 or F=1. Rework the framer implementation to be more flexible and support more framer setting combinations. The new framer implementation performs the mapping in two steps. First it groups samples into frames, as there might be more than one frame per beat. In the second step the frames are distributed onto the lanes. Note that this still results in a single input bit being mapped onto a single output bit and no combinatorial logic is involved. The two step implementation just makes it (hopefully) easier to follow. The only restriction that remains is that number of frames per beat must be integer. This means that F must be either 1, 2 or 4. Supporting partial frames would result in partial sample sets being consumed at the input, which is not supported by input pipeline. The new framer has provisions for handling values for the number of octets per beat other than 4, but this is not exposed as a configuration option yet since the link layer can only handle 4 octets per beat. Making the octets per beat configurable is something for future iterations of the core. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects.
Getting started
This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.
Prerequisites
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Please make sure that you have the required tool version.
How to build a project
For building a projects, you have to use the GNU Make tool. If you're a Windows user please checkout this page, to see how you can install this tool.
To build a project, checkout the latest release, after that just cd to the project that you want to build and run make:
[~]cd projects/fmcomms2/zc706
[~]make
A more comprehensive build guide can be found under the following link: https://wiki.analog.com/resources/fpga/docs/build
Software
In general all the projects have no-OS (baremetal) and a Linux support. See no-OS or Linux for more information.
Which branch should I use?
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If you want to use the most stable code base, always use the latest release branch.
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If you want to use the greatest and latest, check out the master branch.
License
In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.
The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.
See LICENSE for more details. The separate license files cab be found here:
Comprehensive user guide
See HDL User Guide for a more detailed guide.
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