73 lines
3.7 KiB
Plaintext
73 lines
3.7 KiB
Plaintext
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# cn0577
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# pin connections
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set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports ref_clk_p]; #G02 FMC_LPC_CLK1_M2C_P
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set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports ref_clk_n]; #G03 FMC_LPC_CLK1_M2C_N
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set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports dco_p]; #H04 FMC_LPC_CLK0_M2C_P
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set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports dco_n]; #H05 FMC_LPC_CLK0_M2C_N
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set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports da_p]; #H07 FMC_LPC_LA02_P
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set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports da_n]; #H08 FMC_LPC_LA02_N
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set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports db_p]; #H10 FMC_LPC_LA04_P
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set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports db_n]; #H11 FMC_LPC_LA04_N
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set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports clk_p]; #G06 FMC_LPC_LA00_CC_P
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set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports clk_n]; #G07 FMC_LPC_LA00_CC_N
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set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25} [get_ports cnv_p]; #D08 FMC_LPC_LA01_CC_P
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set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25} [get_ports cnv_n]; #D09 FMC_LPC_LA01_CC_N
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set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports cnv_en]; #G10 FMC_LPC_LA03_N
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set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports pd_cntrl]; #G18 FMC_LPC_LA16_P
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set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports testpat_cntrl]; #G21 FMC_LPC_LA20_P
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set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports twolanes_cntrl]; #G24 FMC_LPC_LA22_P
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# 120MHz clock
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set clk_period 8.333
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# differential propagation delay for ref_clk
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set tref_early 0.3
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set tref_late 1.5
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# differential propagation delay for virt_clk
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set tvirt_early 0
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set tvirt_late 0.225
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# data delay
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set data_delay 0.200
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# clocks
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create_clock -period $clk_period -name dco [get_ports dco_p]
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create_clock -period $clk_period -name ref_clk [get_ports ref_clk_p]
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create_clock -period $clk_period -name virt_clk
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# clock latencies
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# minimum source latency values
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set_clock_latency -source -early $tref_early [get_clocks ref_clk]
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set_clock_latency -source -early $tvirt_early [get_clocks virt_clk]
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# maximum source latency values
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set_clock_latency -source -late $tref_late [get_clocks ref_clk]
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set_clock_latency -source -late $tvirt_late [get_clocks virt_clk]
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# input delays
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set_input_delay -clock dco -max $data_delay [get_ports da_p]
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set_input_delay -clock dco -min -$data_delay [get_ports da_p]
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set_input_delay -clock dco -clock_fall -max -add_delay $data_delay [get_ports da_p]
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set_input_delay -clock dco -clock_fall -min -add_delay -$data_delay [get_ports da_p]
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set_input_delay -clock dco -max $data_delay [get_ports db_p]
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set_input_delay -clock dco -min -$data_delay [get_ports db_p]
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set_input_delay -clock dco -clock_fall -max -add_delay $data_delay [get_ports db_p]
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set_input_delay -clock dco -clock_fall -min -add_delay -$data_delay [get_ports db_p]
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# output delays
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set_output_delay -clock [get_clocks virt_clk] -max 2 [get_ports cnv_en]
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set_output_delay -clock [get_clocks virt_clk] -min -0.3 [get_ports cnv_en]
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# multicycle paths
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set_multicycle_path 2 -setup -end -from ref_clk -to virt_clk
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set_multicycle_path 1 -hold -start -from ref_clk -to virt_clk
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set_property IDELAY_VALUE 27 [get_cells i_system_wrapper/system_i/axi_ltc2387/inst/i_if/i_rx_db/i_rx_data_idelay]
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set_property IDELAY_VALUE 27 [get_cells i_system_wrapper/system_i/axi_ltc2387/inst/i_if/i_rx_da/i_rx_data_idelay]
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