253 lines
9.0 KiB
Verilog
253 lines
9.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9671_if (
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// jesd interface
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// rx_clk is (line-rate/40)
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rx_clk,
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rx_sof,
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rx_data,
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// adc data output
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adc_clk,
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adc_rst,
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adc_valid,
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adc_data_a,
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adc_or_a,
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adc_data_b,
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adc_or_b,
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adc_data_c,
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adc_or_c,
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adc_data_d,
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adc_or_d,
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adc_data_e,
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adc_or_e,
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adc_data_f,
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adc_or_f,
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adc_data_g,
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adc_or_g,
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adc_data_h,
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adc_or_h,
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adc_start_code,
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adc_sync_in,
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adc_sync_out,
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adc_sync,
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adc_sync_status,
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adc_status,
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adc_raddr_in,
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adc_raddr_out);
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// parameters
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parameter QUAD_OR_DUAL_N = 1;
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parameter ID = 0;
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// jesd interface
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// rx_clk is (line-rate/40)
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input rx_clk;
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input rx_sof;
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input [(64*QUAD_OR_DUAL_N)+63:0] rx_data;
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// adc data output
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output adc_clk;
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input adc_rst;
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output adc_valid;
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output [ 15:0] adc_data_a;
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output adc_or_a;
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output [ 15:0] adc_data_b;
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output adc_or_b;
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output [ 15:0] adc_data_c;
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output adc_or_c;
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output [ 15:0] adc_data_d;
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output adc_or_d;
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output [ 15:0] adc_data_e;
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output adc_or_e;
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output [ 15:0] adc_data_f;
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output adc_or_f;
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output [ 15:0] adc_data_g;
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output adc_or_g;
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output [ 15:0] adc_data_h;
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output adc_or_h;
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input [ 31:0] adc_start_code;
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input adc_sync_in;
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output adc_sync_out;
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input adc_sync;
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output adc_sync_status;
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output adc_status;
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input [ 3:0] adc_raddr_in;
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output [ 3:0] adc_raddr_out;
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// internal wires
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wire [127:0] adc_wdata;
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wire [127:0] adc_rdata;
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wire [ 15:0] adc_data_a_s;
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wire [ 15:0] adc_data_b_s;
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wire [ 15:0] adc_data_c_s;
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wire [ 15:0] adc_data_d_s;
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wire [ 15:0] adc_data_e_s;
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wire [ 15:0] adc_data_f_s;
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wire [ 15:0] adc_data_g_s;
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wire [ 15:0] adc_data_h_s;
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wire [ 3:0] adc_raddr_s;
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wire adc_sync_s;
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// internal registers
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reg int_valid = 'd0;
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reg [127:0] int_data = 'd0;
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reg adc_status = 'd0;
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reg adc_sync_status = 'd0;
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reg rx_sof_d = 'd0;
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reg [ 3:0] adc_waddr = 'd0;
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reg [ 3:0] adc_raddr_out = 'd0;
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reg [ 15:0] adc_data_a;
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reg [ 15:0] adc_data_b;
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reg [ 15:0] adc_data_c;
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reg [ 15:0] adc_data_d;
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reg [ 15:0] adc_data_e;
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reg [ 15:0] adc_data_f;
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reg [ 15:0] adc_data_g;
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reg [ 15:0] adc_data_h;
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// adc clock & valid
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assign adc_clk = rx_clk;
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assign adc_valid = int_valid;
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assign adc_sync_out = adc_sync;
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assign adc_or_a = 'd0;
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assign adc_or_b = 'd0;
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assign adc_or_c = 'd0;
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assign adc_or_d = 'd0;
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assign adc_or_e = 'd0;
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assign adc_or_f = 'd0;
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assign adc_or_g = 'd0;
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assign adc_or_h = 'd0;
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assign adc_data_a_s = {int_data[ 7: 0], int_data[ 15: 8]};
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assign adc_data_b_s = {int_data[ 23: 16], int_data[ 31: 24]};
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assign adc_data_c_s = {int_data[ 39: 32], int_data[ 47: 40]};
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assign adc_data_d_s = {int_data[ 55: 48], int_data[ 63: 56]};
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assign adc_data_e_s = {int_data[ 71: 64], int_data[ 79: 72]};
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assign adc_data_f_s = {int_data[ 87: 80], int_data[ 95: 88]};
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assign adc_data_g_s = {int_data[103: 96], int_data[111:104]};
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assign adc_data_h_s = {int_data[119:112], int_data[127:120]};
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assign adc_wdata = {adc_data_h_s, adc_data_g_s, adc_data_f_s, adc_data_e_s,
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adc_data_d_s, adc_data_c_s, adc_data_b_s, adc_data_a_s};
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assign adc_raddr_s = (ID == 0) ? adc_raddr_out : adc_raddr_in;
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assign adc_sync_s = (ID == 0) ? adc_sync_out : adc_sync_in;
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always @(posedge rx_clk) begin
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adc_data_a <= adc_rdata[ 15: 0];
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adc_data_b <= adc_rdata[ 31: 16];
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adc_data_c <= adc_rdata[ 47: 32];
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adc_data_d <= adc_rdata[ 63: 48];
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adc_data_e <= adc_rdata[ 79: 64];
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adc_data_f <= adc_rdata[ 95: 80];
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adc_data_g <= adc_rdata[111: 96];
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adc_data_h <= adc_rdata[127:112];
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end
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always @(posedge rx_clk) begin
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if (adc_rst == 1'b1) begin
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adc_waddr <= 4'h0;
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adc_raddr_out <= 4'h8;
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adc_sync_status <= 1'b0;
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end else begin
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if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
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adc_sync_status <= 1'b0;
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end else if(adc_sync_s == 1'b1) begin
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adc_sync_status <= 1'b1;
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end
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if (adc_data_a_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
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adc_waddr <= 4'h0;
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adc_raddr_out <= 4'h8;
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end else if (int_valid == 1'b1) begin
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adc_waddr <= adc_waddr + 1;
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adc_raddr_out <= adc_raddr_out + 1;
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end
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end
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end
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always @(posedge rx_clk) begin
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if (QUAD_OR_DUAL_N == 1'b1) begin
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int_valid <= 1'b1;
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int_data <= rx_data;
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end else begin
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rx_sof_d <= rx_sof;
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int_valid <= rx_sof_d;
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int_data[63:0] <= {rx_data[31:0], int_data[63:32]};
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int_data[127:64] <= {rx_data[63:32], int_data[127:96]};
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end
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end
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always @(posedge rx_clk) begin
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if (adc_rst == 1'b1) begin
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adc_status <= 1'b0;
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end else begin
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adc_status <= 1'b1;
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end
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end
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ad_mem #(.ADDRESS_WIDTH(4), .DATA_WIDTH(128)) i_mem (
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.clka(rx_clk),
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.wea(int_valid),
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.addra(adc_waddr),
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.dina(adc_wdata),
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.clkb(rx_clk),
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.addrb(adc_raddr_s),
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.doutb(adc_rdata));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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