506 lines
16 KiB
Verilog
506 lines
16 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad7616 (
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// physical data interface
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sclk,
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cs_n,
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sdo,
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sdi_0,
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sdi_1,
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db_o,
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db_i,
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db_t,
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rd_n,
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wr_n,
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// physical control interface
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cnvst,
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busy,
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// AXI Slave Memory Map
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rresp,
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s_axi_rdata,
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s_axi_rready,
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// AXI-Stream Master
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m_axis_tdata,
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m_axis_tvalid,
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m_axis_tready,
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m_axis_xfer_req,
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irq
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);
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// parameters
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parameter ID = 0;
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parameter IF_TYPE = 1;
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// local parameters
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localparam DATA_WIDTH = 8;
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localparam NUM_OF_SDI = 2;
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localparam SERIAL = 0;
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localparam PARALLEL = 1;
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localparam NEG_EDGE = 1;
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localparam UP_ADDRESS_WIDTH = 14;
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// IO definitions
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output sclk;
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output cs_n;
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output sdo;
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input sdi_0;
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input sdi_1;
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output [15:0] db_o;
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input [15:0] db_i;
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output db_t;
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output rd_n;
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output wr_n;
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output cnvst;
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input busy;
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [31:0] s_axi_awaddr;
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output s_axi_awready;
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input s_axi_wvalid;
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input [31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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input s_axi_bready;
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input s_axi_arvalid;
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input [31:0] s_axi_araddr;
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output s_axi_arready;
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output s_axi_rvalid;
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output [ 1:0] s_axi_rresp;
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output [31:0] s_axi_rdata;
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input s_axi_rready;
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output [31:0] m_axis_tdata;
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input m_axis_tready;
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output m_axis_tvalid;
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input m_axis_xfer_req;
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output irq;
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// internal registers
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// internal signals
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wire up_clk;
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wire up_rstn;
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wire up_rst;
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wire up_rreq_s;
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wire [(UP_ADDRESS_WIDTH-1):0] up_raddr_s;
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wire up_wreq_s;
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wire [(UP_ADDRESS_WIDTH-1):0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_wack_if_s;
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wire up_rack_if_s;
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wire [31:0] up_rdata_if_s;
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wire up_wack_cntrl_s;
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wire up_rack_cntrl_s;
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wire [31:0] up_rdata_cntrl_s;
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wire trigger_s;
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wire rd_req_s;
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wire wr_req_s;
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wire [15:0] wr_data_s;
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wire [15:0] rd_data_s;
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wire rd_dvalid_s;
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wire [ 4:0] burst_length_s;
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// internal registers
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reg up_wack = 1'b0;
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reg up_rack = 1'b0;
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reg [31:0] up_rdata = 32'b0;
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// defaults
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign up_rst = ~s_axi_aresetn;
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_wack <= up_wack_if_s | up_wack_cntrl_s;
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up_rack <= up_rack_if_s | up_rack_cntrl_s;
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up_rdata <= up_rdata_if_s | up_rdata_cntrl_s;
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end
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end
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generate if (IF_TYPE == SERIAL) begin
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// ground all parallel interface signals
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assign db_o = 16'b0;
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assign rd_n = 1'b0;
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assign wr_n = 1'b0;
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// SPI Framework instances and logic
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wire spi_resetn_s;
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wire s0_cmd_ready_s;
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wire s0_cmd_valid_s;
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wire [15:0] s0_cmd_data_s;
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wire s0_sdo_data_ready_s;
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wire s0_sdo_data_valid_s;
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wire [(DATA_WIDTH-1):0] s0_sdo_data_s;
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wire s0_sdi_data_ready_s;
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wire s0_sdi_data_valid_s;
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wire [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data_s;
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wire s0_sync_ready_s;
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wire s0_sync_valid_s;
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wire [ 7:0] s0_sync_s;
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wire s1_cmd_ready_s;
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wire s1_cmd_valid_s;
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wire [15:0] s1_cmd_data_s;
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wire s1_sdo_data_ready_s;
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wire s1_sdo_data_valid_s;
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wire [(DATA_WIDTH-1):0] s1_sdo_data_s;
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wire s1_sdi_data_ready_s;
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wire s1_sdi_data_valid_s;
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wire [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data_s;
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wire s1_sync_ready_s;
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wire s1_sync_valid_s;
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wire [ 7:0] s1_sync_s;
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wire m_cmd_ready_s;
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wire m_cmd_valid_s;
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wire [15:0] m_cmd_data_s;
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wire m_sdo_data_ready_s;
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wire m_sdo_data_valid_s;
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wire [(DATA_WIDTH-1):0] m_sdo_data_s;
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wire m_sdi_data_ready_s;
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wire m_sdi_data_valid_s;
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wire [(NUM_OF_SDI * DATA_WIDTH-1):0] m_sdi_data_s;
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wire m_sync_ready_s;
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wire m_sync_valid_s;
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wire [ 7:0] m_sync_s;
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wire offload0_cmd_wr_en_s;
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wire [15:0] offload0_cmd_wr_data_s;
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wire offload0_sdo_wr_en_s;
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wire [(DATA_WIDTH-1):0] offload0_sdo_wr_data_s;
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wire offload0_mem_reset_s;
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wire offload0_enable_s;
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wire offload0_enabled_s;
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axi_spi_engine #(
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.DATA_WIDTH (DATA_WIDTH),
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.NUM_OF_SDI (NUM_OF_SDI),
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.NUM_OFFLOAD(1),
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.MM_IF_TYPE(1),
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.UP_ADDRESS_WIDTH (UP_ADDRESS_WIDTH)
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) i_axi_spi_engine(
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_if_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_if_s),
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.up_rack (up_rack_if_s),
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.irq (irq),
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.spi_clk (up_clk),
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.spi_resetn (spi_resetn_s),
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.cmd_ready (s0_cmd_ready_s),
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.cmd_valid (s0_cmd_valid_s),
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.cmd_data (s0_cmd_data_s),
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.sdo_data_ready (s0_sdo_data_ready_s),
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.sdo_data_valid (s0_sdo_data_valid_s),
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.sdo_data (s0_sdo_data_s),
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.sdi_data_ready (s0_sdi_data_ready_s),
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.sdi_data_valid (s0_sdi_data_valid_s),
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.sdi_data (s0_sdi_data_s),
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.sync_ready (s0_sync_ready_s),
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.sync_valid (s0_sync_valid_s),
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.sync_data (s0_sync_s),
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.offload0_cmd_wr_en (offload0_cmd_wr_en_s),
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.offload0_cmd_wr_data (offload0_cmd_wr_data_s),
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.offload0_sdo_wr_en (offload0_sdo_wr_en_s),
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.offload0_sdo_wr_data (offload0_sdo_wr_data_s),
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.offload0_mem_reset (offload0_mem_reset_s),
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.offload0_enable (offload0_enable_s),
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.offload0_enabled(offload0_enabled_s));
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spi_engine_offload #(
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.DATA_WIDTH (DATA_WIDTH),
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.NUM_OF_SDI (NUM_OF_SDI)
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) i_spi_engine_offload(
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.ctrl_clk (up_clk),
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.ctrl_cmd_wr_en (offload0_cmd_wr_en_s),
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.ctrl_cmd_wr_data (offload0_cmd_wr_data_s),
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.ctrl_sdo_wr_en (offload0_sdo_wr_en_s),
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.ctrl_sdo_wr_data (offload0_sdo_wr_data_s),
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.ctrl_enable (offload0_enable_s),
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.ctrl_enabled (offload0_enabled_s),
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.ctrl_mem_reset (offload0_mem_reset_s),
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.spi_clk (up_clk),
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.spi_resetn (spi_resetn_s),
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.trigger (trigger_s),
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.cmd_valid (s1_cmd_valid_s),
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.cmd_ready (s1_cmd_ready_s),
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.cmd (s1_cmd_data_s),
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.sdo_data_valid (s1_sdo_data_valid_s),
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.sdo_data_ready (s1_sdo_data_ready_s),
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.sdo_data (s1_sdo_data_s),
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.sdi_data_valid (s1_sdi_data_valid_s),
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.sdi_data_ready (s1_sdi_data_ready_s),
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.sdi_data (s1_sdi_data_s),
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.sync_valid (s1_sync_valid_s),
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.sync_ready (s1_sync_ready_s),
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.sync_data (s1_sync_s),
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.offload_sdi_valid (m_axis_tvalid),
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.offload_sdi_ready (m_axis_tready),
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.offload_sdi_data (m_axis_tdata));
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spi_engine_interconnect #(
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.DATA_WIDTH (DATA_WIDTH),
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.NUM_OF_SDI (NUM_OF_SDI)
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) i_spi_engine_interconnect (
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.clk (up_clk),
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.resetn (spi_resetn_s),
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.m_cmd_valid (m_cmd_valid_s),
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.m_cmd_ready (m_cmd_ready_s),
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.m_cmd_data (m_cmd_data_s),
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.m_sdo_valid (m_sdo_data_valid_s),
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.m_sdo_ready (m_sdo_data_ready_s),
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.m_sdo_data (m_sdo_data_s),
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.m_sdi_valid (m_sdi_data_valid_s),
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.m_sdi_ready (m_sdi_data_ready_s),
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.m_sdi_data (m_sdi_data_s),
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.m_sync_valid (m_sync_valid_s),
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.m_sync_ready (m_sync_ready_s),
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.m_sync (m_sync_s),
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.s0_cmd_valid (s0_cmd_valid_s),
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.s0_cmd_ready (s0_cmd_ready_s),
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.s0_cmd_data (s0_cmd_data_s),
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.s0_sdo_valid (s0_sdo_data_valid_s),
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.s0_sdo_ready (s0_sdo_data_ready_s),
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.s0_sdo_data (s0_sdo_data_s),
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.s0_sdi_valid (s0_sdi_data_valid_s),
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.s0_sdi_ready (s0_sdi_data_ready_s),
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.s0_sdi_data (s0_sdi_data_s),
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.s0_sync_valid (s0_sync_valid_s),
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.s0_sync_ready (s0_sync_ready_s),
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.s0_sync (s0_sync_s),
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.s1_cmd_valid (s1_cmd_valid_s),
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.s1_cmd_ready (s1_cmd_ready_s),
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.s1_cmd_data (s1_cmd_data_s),
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.s1_sdo_valid (s1_sdo_data_valid_s),
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.s1_sdo_ready (s1_sdo_data_ready_s),
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.s1_sdo_data (s1_sdo_data_s),
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.s1_sdi_valid (s1_sdi_data_valid_s),
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.s1_sdi_ready (s1_sdi_data_ready_s),
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.s1_sdi_data (s1_sdi_data_s),
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.s1_sync_valid (s1_sync_valid_s),
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.s1_sync_ready (s1_sync_ready_s),
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.s1_sync (s1_sync_s));
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spi_engine_execution #(
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.DATA_WIDTH (DATA_WIDTH),
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.NUM_OF_SDI (NUM_OF_SDI)
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) i_spi_engine_execution (
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.clk (up_clk),
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.resetn (spi_resetn_s),
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.active (),
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.cmd_ready (m_cmd_ready_s),
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.cmd_valid (m_cmd_valid_s),
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.cmd (m_cmd_data_s),
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.sdo_data_valid (m_sdo_data_valid_s),
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.sdo_data_ready (m_sdo_data_ready_s),
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.sdo_data (m_sdo_data_s),
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.sdi_data_ready (m_sdi_data_ready_s),
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.sdi_data_valid (m_sdi_data_valid_s),
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.sdi_data (m_sdi_data_s),
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.sync_ready (m_sync_ready_s),
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.sync_valid (m_sync_valid_s),
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.sync (m_sync_s),
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.sclk (sclk),
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.sdo (sdo),
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.sdo_t (),
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.sdi (sdi_0),
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.sdi_1 (sdi_1),
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.sdi_2 (1'b0),
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.sdi_3 (1'b0),
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.cs (cs_n),
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.three_wire ());
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end
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endgenerate
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generate if (IF_TYPE == PARALLEL) begin
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assign sclk = 1'h0;
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assign sdo = 1'h0;
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assign irq = 1'h0;
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assign up_wack_if_s = 1'h0;
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assign up_rack_if_s = 1'h0;
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assign up_rdata_if_s = 1'h0;
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axi_ad7616_pif i_ad7616_parallel_interface (
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.cs_n(cs_n),
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.db_o(db_o),
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.db_i(db_i),
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.db_t(db_t),
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.rd_n(rd_n),
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.wr_n(wr_n),
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.m_axis_tdata(m_axis_tdata),
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.m_axis_tvalid(m_axis_tvalid),
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.m_axis_tready(m_axis_tready),
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.m_axis_xfer_req(m_axis_xfer_req),
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.end_of_conv(trigger_s),
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.burst_length(burst_length_s),
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.clk(up_clk),
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.rstn(up_rstn),
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.rd_req(rd_req_s),
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.wr_req(wr_req_s),
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.wr_data(wr_data_s),
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.rd_data(rd_data_s),
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.rd_dvalid(rd_dvalid_s)
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);
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end
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endgenerate
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axi_ad7616_control #(
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.ID(ID),
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.IF_TYPE(IF_TYPE)
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) i_ad7616_control (
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.cnvst (cnvst),
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.busy (busy),
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.up_burst_length (burst_length_s),
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.up_read_data (rd_data_s),
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.up_read_valid (rd_dvalid_s),
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.up_write_data (wr_data_s),
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.up_read_req (rd_req_s),
|
|
.up_write_req (wr_req_s),
|
|
.end_of_conv (trigger_s),
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_wreq (up_wreq_s),
|
|
.up_waddr (up_waddr_s),
|
|
.up_wdata (up_wdata_s),
|
|
.up_wack (up_wack_cntrl_s),
|
|
.up_rreq (up_rreq_s),
|
|
.up_raddr (up_raddr_s),
|
|
.up_rdata (up_rdata_cntrl_s),
|
|
.up_rack (up_rack_cntrl_s));
|
|
|
|
// up bus interface
|
|
|
|
up_axi #(
|
|
.ADDRESS_WIDTH (UP_ADDRESS_WIDTH)
|
|
) i_up_axi (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_axi_awvalid (s_axi_awvalid),
|
|
.up_axi_awaddr (s_axi_awaddr),
|
|
.up_axi_awready (s_axi_awready),
|
|
.up_axi_wvalid (s_axi_wvalid),
|
|
.up_axi_wdata (s_axi_wdata),
|
|
.up_axi_wstrb (s_axi_wstrb),
|
|
.up_axi_wready (s_axi_wready),
|
|
.up_axi_bvalid (s_axi_bvalid),
|
|
.up_axi_bresp (s_axi_bresp),
|
|
.up_axi_bready (s_axi_bready),
|
|
.up_axi_arvalid (s_axi_arvalid),
|
|
.up_axi_araddr (s_axi_araddr),
|
|
.up_axi_arready (s_axi_arready),
|
|
.up_axi_rvalid (s_axi_rvalid),
|
|
.up_axi_rresp (s_axi_rresp),
|
|
.up_axi_rdata (s_axi_rdata),
|
|
.up_axi_rready (s_axi_rready),
|
|
.up_wreq (up_wreq_s),
|
|
.up_waddr (up_waddr_s),
|
|
.up_wdata (up_wdata_s),
|
|
.up_wack (up_wack),
|
|
.up_rreq (up_rreq_s),
|
|
.up_raddr (up_raddr_s),
|
|
.up_rdata (up_rdata),
|
|
.up_rack (up_rack));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|