| .. |
|
altera
|
avl_dacfifo: Update constraints
|
2017-04-21 17:25:46 +03:00 |
|
axi_ad6676
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_ad7616
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_ad9122
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_ad9144
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_ad9152
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_ad9162
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_ad9234
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_ad9250
|
axi_ad9250: Port redeclaration as a wire is not allowed
|
2017-04-20 10:50:21 +03:00 |
|
axi_ad9265
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_ad9361
|
axi_ad9361: Fix Warning[Synth 8-2611]
|
2017-04-19 13:52:13 +03:00 |
|
axi_ad9371
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_ad9434
|
axi_ad9434: ad_serdes_clk instantiation should reflect all important configurations
|
2017-04-20 18:52:06 +03:00 |
|
axi_ad9467
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_ad9625
|
axi_ad9625: Port redeclaration as a wire is not allowed
|
2017-04-20 10:49:24 +03:00 |
|
axi_ad9643
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_ad9652
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_ad9671
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_ad9680
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_ad9684
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_ad9739a
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_ad9963
|
axi_ad9963: Integrated ADC/DAC clock enables
|
2017-04-18 12:17:40 +02:00 |
|
axi_adc_decimate
|
axi_adc_decimate: Reduce AXI address width
|
2017-04-18 12:17:41 +02:00 |
|
axi_adc_trigger
|
axi_adc_trigger: Reduce AXI address width
|
2017-04-18 12:17:41 +02:00 |
|
axi_clkgen
|
axi_clkgen: Propagate clock settings to output pins
|
2017-04-20 20:36:33 +02:00 |
|
axi_dac_interpolate
|
axi_dac_interpolate: Reduce AXI address width
|
2017-04-18 12:17:41 +02:00 |
|
axi_dmac
|
axi_dmac: post_propagate(): Handle mappings with multiple address segments
|
2017-04-19 13:47:02 +02:00 |
|
axi_generic_adc
|
updated makefiles
|
2016-12-09 23:06:41 +02:00 |
|
axi_gpreg
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_hdmi_rx
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
axi_hdmi_tx
|
axi_hdmi_tx: Fix assignment type
|
2017-04-21 09:35:34 +03:00 |
|
axi_i2s_adi
|
library: axi_i2s_adi, axi_spdif_rx, axi_spdif_tx, util_axis_fifo rename ports to lowercase
|
2017-04-18 12:17:41 +02:00 |
|
axi_intr_monitor
|
updated makefiles
|
2016-12-09 23:06:41 +02:00 |
|
axi_logic_analyzer
|
axi_logic_analyzer: Reduce AXI address width
|
2017-04-18 12:17:40 +02:00 |
|
axi_mc_controller
|
library: Delete all adi_ip_constraint process call
|
2017-04-06 12:36:47 +03:00 |
|
axi_mc_current_monitor
|
library: Delete all adi_ip_constraint process call
|
2017-04-06 12:36:47 +03:00 |
|
axi_mc_speed
|
library: Delete all adi_ip_constraint process call
|
2017-04-06 12:36:47 +03:00 |
|
axi_rd_wr_combiner
|
Add a helper module to combine a AXI read-only and a AXI write-only interface into a read-write interface
|
2017-04-18 12:17:39 +02:00 |
|
axi_spdif_rx
|
library: axi_i2s_adi, axi_spdif_rx, axi_spdif_tx, util_axis_fifo rename ports to lowercase
|
2017-04-18 12:17:41 +02:00 |
|
axi_spdif_tx
|
library: axi_i2s_adi, axi_spdif_rx, axi_spdif_tx, util_axis_fifo rename ports to lowercase
|
2017-04-18 12:17:41 +02:00 |
|
axi_usb_fx3
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
cn0363
|
updated makefiles
|
2016-12-09 23:06:41 +02:00 |
|
common
|
axi_dacfifo: Move the axi_dac_fifo_bypass module to util_dac_fifo_bypass
|
2017-04-21 13:23:03 +03:00 |
|
cordic_demod
|
updated makefiles
|
2016-12-09 23:06:41 +02:00 |
|
interfaces
|
interfaces- remove channel based pll reset
|
2016-11-22 11:34:29 -05:00 |
|
prcfg
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
scripts
|
scripts/adi_ip.pl: Infer register map range from address width
|
2017-04-18 12:17:40 +02:00 |
|
spi_engine
|
spi_engine: Fix CMD_FIFO_VALID generation
|
2017-04-12 14:57:22 +02:00 |
|
util_adcfifo
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
util_axis_fifo
|
library: axi_i2s_adi, axi_spdif_rx, axi_spdif_tx, util_axis_fifo rename ports to lowercase
|
2017-04-18 12:17:41 +02:00 |
|
util_axis_resize
|
updated makefiles
|
2016-12-09 23:06:41 +02:00 |
|
util_bsplit
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
util_ccat
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
util_cic
|
util_cic: Allow partial gating of CIC comb and int stages
|
2017-04-18 12:17:40 +02:00 |
|
util_clkdiv
|
library: Delete all adi_ip_constraint process call
|
2017-04-06 12:36:47 +03:00 |
|
util_cpack
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
util_dacfifo
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
util_extract
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
util_fir_dec
|
util_fir_dec: Changed output rounding mode to Symmetric rounding to Zero
|
2017-03-09 16:33:17 +02:00 |
|
util_fir_int
|
util_fir_int: Shifted data so that the amplitude at the output of the filter is the same with the input
|
2017-03-08 14:29:26 +02:00 |
|
util_gmii_to_rgmii
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
util_i2c_mixer
|
updated makefiles
|
2016-12-09 23:06:41 +02:00 |
|
util_mfifo
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
util_pmod_adc
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
util_pmod_fmeter
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
util_rfifo
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
util_sigma_delta_spi
|
updated makefiles
|
2016-12-09 23:06:41 +02:00 |
|
util_tdd_sync
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
util_upack
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
util_var_fifo
|
util_var_fifo: Assign data_out and data_out_valid based on fifo_active
|
2017-04-18 12:17:40 +02:00 |
|
util_wfifo
|
all: Update verilog files to verilog-2001
|
2017-04-13 11:59:55 +03:00 |
|
xilinx
|
axi_dacfifo: Fix Makefile
|
2017-04-24 11:46:29 +03:00 |
|
Makefile
|
Add CIC filter helper module
|
2017-04-18 12:17:40 +02:00 |
4f4ca84813